EVAL-AD5372EBZ Analog Devices Inc, EVAL-AD5372EBZ Datasheet - Page 6

• Manufacturer Part Number: EVAL-AD5372EBZ
• Description: BOARD EVAL FOR AD5372
• Manufacturer: Analog Devices Inc

Specifications of EVAL-AD5372EBZ

• Number Of Dac's: 32
• Number Of Bits: 16
• Outputs And Type: 32, Single Ended
• Sampling Rate (per Second): 540k
• Data Interface: Serial
• Settling Time: 20µs
• Dac Type: Voltage
• Voltage Supply Source: Dual ±
• Operating Temperature: -40°C ~ 85°C
• Utilized Ic / Part: AD5372
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AD5372/AD5373
TIMING CHARACTERISTICS
DV
R
Table 4. SPI Interface
Parameter
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
1
2
3
4
5
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
Guaranteed by design and characterization; not production tested.
All input signals are specified with t
See Figure 4 and Figure 5.
t
t
L
4
9
22
5
is measured with the load circuit shown in Figure 2
= open circuit; gain (M), offset (C), and DAC offset registers at default values; all specifications T
is measured with the load circuit shown in Figure 3.
CC
= 2.5 V to 5.5 V; V
1, 2, 3
Figure 2. Load Circuit for BUSY Timing Diagram
OUTPUT
Limit at T
20
8
8
11
20
10
5
5
42
1/1.5
600
20
10
3
0
3
20/30
140
30
400
270
25
80
PIN
TO
DD
= 9 V to 16.5 V; V
R
= t
MIN
DV
F
, T
= 2 ns (10% to 90% of DV
C
50pF
CC
L
R
2.2kΩ
MAX
L
SS
V
.
OL
= −16.5 V to −8 V; VREFx = 3 V; AGND = DGND = SIGGNDx = 0 V; C
Unit
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns max
μs typ/μs max
ns max
ns min
ns min
μs max
ns min
μs max
μs typ/μs max
ns max
ns min
μs max
ns min
ns max
ns max
CC
) and timed from a voltage level of 1.2 V.
Rev. B | Page 6 of 24
Description
SCLK cycle time
SCLK high time
SCLK low time
SYNC falling edge to SCLK falling edge setup time
Minimum SYNC high time
24
Data setup time
Data hold time
SYNC rising edge to BUSY falling edge
BUSY pulse width low (single-channel update); see Table 9
Single-channel update cycle time
SYNC rising edge to LDAC falling edge
LDAC pulse width low
BUSY rising edge to DAC output response time
BUSY rising edge to LDAC falling edge
LDAC falling edge to DAC output response time
DAC output settling time
CLR/RESET pulse activation time
RESET pulse width low
RESET time indicated by BUSY low
Minimum SYNC high time in readback mode
SCLK rising edge to SDO valid
RESET rising edge to BUSY falling edge
th
SCLK falling edge to SYNC rising edge
TO OUTPUT
PIN
Figure 3. Load Circuit for SDO Timing Diagram
50pF
C
L
200µA
200µA
MIN
I
I
OL
OH
to T
MAX
, unless otherwise noted.
V
OH
(MIN) – V
L
= 200 pF to GND;
2
OL
(MAX)