EVAL-AD5373EBZ Analog Devices Inc, EVAL-AD5373EBZ Datasheet - Page 21

• Manufacturer Part Number: EVAL-AD5373EBZ
• Description: BOARD EVAL FOR AD5373
• Manufacturer: Analog Devices Inc

Specifications of EVAL-AD5373EBZ

• Number Of Dac's: 32
• Number Of Bits: 14
• Outputs And Type: 32, Single Ended
• Sampling Rate (per Second): 540k
• Data Interface: Serial
• Settling Time: 20µs
• Dac Type: Voltage
• Voltage Supply Source: Dual ±
• Operating Temperature: -40°C ~ 85°C
• Utilized Ic / Part: AD5373
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

CHANNEL ADDRESSING AND SPECIAL MODES
If the mode bits are not 00, the data-word D15 to D0 (AD5372)
or D13 to D0 (AD5373) is written to the device. Address Bit A5
to Address Bit A0 determine which channels are written to, and
the mode bits determine to which register (X1A, X1B, C, or M)
the data is written, as shown in Table 13 and Table 14. Data is to
be written to the X1A register when the A /B bit in the control
register is 0, or to the X1B register when the A /B bit is 1.
The AD5372/AD5373 have very flexible addressing that allows
the writing of data to a single channel, all channels in a group,
the same channel in Group 0 to Group 3, the same channel in
Group 1 to Group 3, or all channels in the device. Table 14 shows
which groups and which channels are addressed for every
combination of Address Bit A5 to Address Bit A0.
Table 14. Group and Channel Addressing
Address Bit A2
to Address Bit A0
000
001
010
011
100
101
110
111
000
All groups,
all channels
Group 0, all
channels
Group 1, all
channels
Group 2, all
channels
Group 3, all
channels
Reserved
Reserved
Reserved
001
Group 0,
Channel 0
Group 0,
Channel 1
Group 0,
Channel 2
Group 0,
Channel 3
Group 0,
Channel 4
Group 0,
Channel 5
Group 0,
Channel 6
Group 0,
Channel 7
010
Group 1,
Channel 0
Group 1,
Channel 1
Group 1,
Channel 2
Group 1,
Channel 3
Group 1,
Channel 4
Group 1,
Channel 5
Group 1,
Channel 6
Group 1,
Channel 7
Rev. B | Page 21 of 24
Address Bit A5 to Address Bit A3
011
Group 2,
Channel 0
Group 2,
Channel 1
Group 2,
Channel 2
Group 2,
Channel 3
Group 2,
Channel 4
Group 2,
Channel 5
Group 2,
Channel 6
Group 2,
Channel 7
Table 13. Mode Bits
M1
1
1
0
0
M0
1
0
1
0
100
Group 3,
Channel 0
Group 3,
Channel 1
Group 3,
Channel 2
Group 3,
Channel 3
Group 3,
Channel 4
Group 3,
Channel 5
Group 3,
Channel 6
Group 3,
Channel 7
Write to DAC offset (C) register
Action
Write to DAC data (X) register
Write to DAC gain (M) register
Special function, used in combination with other
bits of the data-word
101
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
110
Group 0,
Group 1,
Group 2,
Group 3;
Channel 0
Group 0,
Group 1,
Group 2,
Group 3;
Channel 1
Group 0,
Group 1,
Group 2,
Group 3;
Channel 2
Group 0,
Group 1,
Group 2,
Group 3;
Channel 3
Group 0,
Group 1,
Group 2,
Group 3;
Channel 4
Group 0,
Group 1,
Group 2,
Group 3;
Channel 5
Group 0,
Group 1,
Group 2,
Group 3;
Channel 6
Group 0,
Group 1,
Group 2,
Group 3;
Channel 7
AD5372/AD5373
111
Group 1,
Group 2,
Group 3;
Channel 0
Group 1,
Group 2,
Group 3;
Channel 1
Group 1,
Group 2,
Group 3;
Channel 2
Group 1,
Group 2,
Group 3;
Channel 3
Group 1,
Group 2,
Group 3;
Channel 4
Group 1,
Group 2,
Group 3;
Channel 5
Group 1,
Group 2,
Group 3;
Channel 6
Group 1,
Group 2,
Group 3;
Channel 7