MAX5661EVCMAXQU+ Maxim Integrated Products, MAX5661EVCMAXQU+ Datasheet - Page 18

• Manufacturer Part Number: MAX5661EVCMAXQU+
• Description: EVALUATION SYSTEM FOR MAX56611
• Manufacturer: Maxim Integrated Products

Specifications of MAX5661EVCMAXQU+

• Number Of Dac's: 1
• Number Of Bits: 16
• Outputs And Type: 2, Single Ended
• Data Interface: Serial
• Dac Type: Current/Voltage
• Voltage Supply Source: Single
• Operating Temperature: -40°C ~ 105°C
• Utilized Ic / Part: MAX5661
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Single 16-Bit DAC with Current and Voltage
Outputs for Industrial Analog Output Modules
18
54, 59
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PIN
22
23
24
25
26
27
28
35
37
39
40
41
43
45
53
55
56
57
60
V DDCORE
DUTGNDS
DUTGND
COMPV
FAULT
NAME
DGND
AGND
DOUT
LDAC
OUTV
V DDV
SCLK
V SSV
V CC
CLR
SVN
SVP
DIN
I.C.
CS
Serial-Data Input. Data is clocked into the serial interface on the rising edge of SCLK.
Serial-Clock Input
Active-Low Chip-Select Input. Drive CS low to enable the serial interface. Drive CS high to disable
the serial interface. DOUT is high impedance when CS is high.
Digital Ground
Digital Power Supply. Connect V
with a 0.1µF capacitor to DGND, as close as possible to the device.
Active-Low Asynchronous Load DAC Input. Drive LDAC low to transfer the contents of the input
register to the DAC register to immediately update the output. Connect LDAC to V
Active-Low Open-Drain Fault Output. FAULT asserts low for an OUTI open-circuit condition, an
OUTV short-circuit condition, or when the CLR input is low (see Table 12 and Figure 9). Ignore the
FAULT pin function in single supply mode.
Serial Data Output. Data transitions at DOUT on SCLK’s falling edge. DOUT is high impedance
when CS is high. Use DOUT to read the shift register contents or for daisy chaining multiple
MAX5661 devices.
Active-Low Clear Input. Drive CLR low to set the DAC code to the value stored in the clear
register, to 0V in voltage mode, or 0mA/4mA depending on the output current mode. Program the
contents of the clear register through the serial interface. Enable and disable the CLR input
through the control register’s CLREN bit (see Table 4).
DAC Core Positive Supply. Connect V
with a 0.1µF capacitor to AGND, as close as possible to the device.
DUT Analog Sense Ground. Connect DACGND, DACGNDS, DUTGND, and DUTGNDS together
on a low-noise ground plane with a star connection.
DUT Analog Ground. Connect DACGND, DACGNDS, DUTGND, and DUTGNDS together on a
low-noise ground plane with a star connection.
OUTV Amplifier Compensation Feedback Node. Connect a 3.3nF capacitor from OUTV to COMPV
when OUTV drives capacitive loads of up to 1.2µF. Leave COMPV open for faster response time.
Analog Ground
Remote Ground Sense Input. Connect SVP to the bottom terminal of R
Operating Circuit.
Internal Connection. Leave unconnected.
D AC V ol tag e- Outp ut N eg ati ve P ow er S up p l y. Al w ays connect V
and -15.75V. Bypass V
DAC Unipolar/Bipolar Voltage Output. OUTV provides 0 to +10.48V in unipolar mode and -10.48V
to +10.48V in bipolar mode.
DAC Voltage-Output Positive Power Supply. Connect V
and +15.75V. Bypass V
Rem ote V ol tag e S ense Inp ut. C onnect to the top ter m i nal of R
SSV
DDV
with a 0.1µF capacitor to AGND, as close as possible to the device.
with a 0.1µF capacitor to AGND, as close as possible to the device.
CC
to a power supply between +4.75V and +5.25V. Bypass V
DDCORE
FUNCTION
to V
Pin Description (continued)
DDI
or V
DDV
DDV
OU T V
to a power supply between +13.48V
S S V
(see Table 16). Bypass V
to a p ow er sup p l y b etw een - 13.48V
. S ee the Typ i cal Op er ati ng C i r cui t.
OUTV
. See the Typical
CC
if unused.
DDCORE
CC