SI85XX-EVB Silicon Laboratories Inc, SI85XX-EVB Datasheet
SI85XX-EVB
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SI85XX-EVB Summary of contents
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... Description The Si85xx products are unidirectional ac current sensors available in full-scale ranges of 5, 10, and 20 A. Si85xx products are ideal upgrades for older current- sensing technologies offering size, performance, and cost advantages over current transformers, Hall effect devices, DCR circuits, and other approaches. The Si85xx are extremely low-loss, adding less than 1.3 m ...
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... Si85xx 2 Preliminary Rev. 0.21 ...
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... Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 7. Package Outline—12-Pin QFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 8. Recommended PCB Landing Pattern (12-Pin QFN Top Marking (QFN 10. Package Outline: Wide Body SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 11. Recommended PCB Landing Pattern (20-Pin SOIC 12. Top Marking (SOIC Document Change List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36 Preliminary Rev. 0.21 Si85xx Page 3 ...
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... Si85xx 1. Electrical Specifications Table 1. Electrical Specifications T = –40 to +125 ºC (typical specified at 25 ºC), VDD = 3 V (±10 (±10%), f = 400 kHz, unless specified A Parameter Supply Voltage ( Supply Current Undervoltage Lockout (V ) UVLO Undervoltage Lockout Hysteresis (V ) HYST Logic Input HIGH Level Logic Input LOW Level ...
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... Permanent device damage may occur if the absolute maximum ratings are exceeded. Functional operation should be restricted to conditions as specified in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2. Refer to “AN329: Extending the Full-Scale Range of the Si85xx” for more information. Conditions Current flow from I ...
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... Input Capacitance Notes determine resistance and capacitance, the Si85xx is converted into a 2-terminal device. Pins 1–10 are shorted together to form the first terminal and pins 11–20 are shorted together to form the second terminal. The parameters are then measured between these two terminals. ...
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... S IO *Note: The Si85xx is suitable for basic and reinforced electrical isolation only within the safety limit data. Maintenance of the safety data is ensured by protective circuits. The Si85xx provides a climate classification of 40/125/21. Note that the Si85xx is compliant with the IEC60747-5-2 but neither certified nor inspected to IEC60747-5-2. The Si85xx is compliant, certified, and factory-inspected to IEC60950 ...
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... Si85xx Table 8. Thermal Characteristics Parameter IC Junction-to-Air Thermal Resistance Figure 1. SOIC-20 Thermal Derating Curve, Dependence of Safety Limiting Values with Case Temperature per DIN EN 60747-5-2 8 Symbol Test Condition JA VDD = 5.5 V IIN to IOUT = 20 Amps 50 100 150 Case Temperature (ºC) Preliminary Rev. 0.21 SOIC-20 ...
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... Low loss: The Si85xx adds only 1.3 m (at 25 °C) to the sensing path, making it one of the lowest-loss current sensors available. Low 2 nH primary series inductance is 2,000 times lower compared and results in significantly less ringing ...
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... Figure 4. Si85xx Startup and Control Timing 10 2.3. Integrator Reset and Current Measurement The Si85xx measures current flowing from the IIN to IOUT terminals. Current is allowed to flow in the opposite direction, but will not be measured (OUT1 and OUT 2 remain at their minimum values during reverse current flow ...
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... Integrator reset Option 1 is selected by connecting T to VDD. In this mode, the Si85xx is held in reset as long as the signals on R1–R4 satisfy the logic equations of Table 11 typically used in applications where the gate drivers are external to the system controller IC (the gate driver delay ensures reset is completed prior to the start of measurement) ...
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... The effect of this error is summarized in Figure 6. The chart is referenced to 25 °C. If the Si85xx is powered °C and then operated at 125 °C with no auto- calibration performed (i.e., the power is not cycled at 125 ° ...
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... Recommended bypass capacitors are 1 µF in parallel with a 0.1 µF, positioned as close to the Si85xx as possible. When using the Si850x (single output versions), all 3 ground pins MUST be connected to the same ground point, and both VDD and VDD2 pins MUST be tied to VDD ...
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... Configuring integrator reset timing 3. Setting integrator reset time t R 3.3.1. Device Selection The Si85xx family offers three output modes: Single output (Si850x), and 2 and 4-Wire Ping Pong (Si851x). The Si851x products can be configured to operate in all three of these output modes. The Si850x products operate ONLY in Single output mode ...
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... This reset must be synchronized with the system switch timing signals to ensure that current is measured during the appropriate time; so, the Si85xx integrator reset circuitry uses system timing as its reference. Timing signals connect to reset inputs R1 through R4 where built-in logic functions allow the user to choose the conditions that cause an integrator reset event. Important Note: reset inputs R1– ...
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... Si85xx Table 11. Si85xx Output and Reset Mode Summary Output Mode MODE R4 Single-Ended 1 0 2-Wire Ping Pong 4-Wire Ping Pong 0 1 *Note: Device is in reset when Reset State = Reset State Preliminary Rev. 0.21 Reset Logic Expression RESET = XOR[R1, (R2|R3)] RESET = XNOR[R1,(R2|R3)] ...
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... MODE = TRST = VDD Output 1 Reset timing determined only by inputs R1–R4. MODE = 1 RESET Output 2 TIMER PGM OUT CLK MODE = 0 Output 3 Preliminary Rev. 0.21 Si85xx TRST = R1 to GND Reset triggered by inputs R1–R4. Reset time (t ) set R by value of resistor R . TRST TRST + 1 0 VREF INTEGRATOR 17 ...
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... Because this timer is re-triggerable, R1–R4 must remain TRUE for the duration of the desired t Figure 14. Should R1–R4 transition FALSE during t measurement accuracy due to higher integrator offset error. CURRENT R1–R4 STATE Si85xx STATUS Si85xx OUTPUT Figure 14. Correct integrator reset will be immediately halted, resulting in lower R R1– ...
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... Output Reset Logic FAULT Output Output Reset Logic FAULT Output Figure 15. Measurement Watchdog Timer Operation t Cycle Reset 30-80 µs FAULT Detect Time FAULT Condition 1 30-80 µs FAULT Detect Time FAULT Condition 2 Preliminary Rev. 0.21 Si85xx 19 ...
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... Si85xx 3.3.6. Output Over-Range The Si85xx can be over-ranged by more than 100% with no adverse effects. For instance, if the Si8512 ( nominal full-scale device) has peak current applied, then the output voltage (OUT) will (assuming VDD = 5 V peak current is applied, then the output returns to the nominal 2 V output. The head room of OUT is VDD– ...
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... TRST R1 PH1 PH2 Figure 17. Si850x Single-Phase Buck Converter R VIN VDD2 GND1 IIN GND2 GND3 Si850x OUT IOUT Q1 L1 VOUT C3 Q2 Si850x State Preliminary Rev. 0.21 Si85xx – 0 200 ns at 80% 2 Vpp PWM PH2 Current > 0 RESET MEASURE 100 ns 21 ...
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... VIN). The external driver delay ensures reset is complete prior to the start of measurement. 22 VIN IIN OUT1 PH1 OUT1 OUT2 OUT2 VDD PH2 TRST IOUT PH3 PH4 Q1 Switches Turned ON Q2 Si85xx State TI OUT1 Q3 Q4 OUT2 Figure 18. Full-Bridge Converter value of 0 Preliminary Rev. 0.21 1–4 1–2 2–3 3–4 MEASURE RESET MEASURE RESET 3 = 6.6 µ ...
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... MODE IIN OUT1 R4 Si851x TRST OUT2 R3 GND R1 IOUT R2 PH2 PH1 Figure 19. Push-Pull Example Using Default t (250 ns). Assuming an 80% maximum duty cycle, this value PH1 PH2 T1 MEASURE Si85xx Status OUT1 Q2 OUT2 Preliminary Rev. 0.21 Si85xx would R RESET MEASURE RESET MEASURE Value R 23 ...
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... Si85xx 4. Pin Descriptions—12-Pin QFN R1 R2 GND2 Si850x GND3 OUT NC Figure 20. Example Pin Configurations Table 12. Si85xx Family Pin Descriptions Pin# Si850x Description Pin Name 1 R1 Integrator reset input Integrator reset input 2 3 GND2 Ground 4 GND3 5 OUT Output connect 7 TRST Reset time control ...
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... Pin Descriptions—20-Pin SOIC 20-Pin SOIC VDD1 VDD2 R1 R2 GND2 Si850x GND3 OUT NC TRST GND1 Figure 21. Example Pin Configurations Table 13. Si85xx Family Pin Descriptions Pin# Si850x Description Pin Name 1 VDD1 Power supply input 2 VDD2 3 R1 Integrator reset input Integrator reset input 2 ...
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... Si85xx 6. Ordering Guide New Full Scale Initial Current Accuracy OPNs ( Si8501-C-IM 5 Si8502-C-IM 10 Si8503-C-IM 20 Si8501-C-IS 5 Si8502-C-IS 10 Si8503-C-IS 20 Si8511-C-IM 5 Si8512-C-IM 10 Si8513-C- Si8511-C-IS 5 Si8512-C-IS 10 Si8513-C-IS 20 Si8517-C-IM 5 Si8518-C-IM 10 Si8519-C-IM 20 Si8517-C-IS 5 Si8518-C-IS 10 Si8519-C-IS 20 Notes: 1. See "2.4. Total Measurement Error" on page 11 for more information. 2. All packages are RoHS-compliant. Moisture Sensitivity level is MSL3 with peak reflow temperature of 260 °C according to the JEDEC industry classification, and peak solder temperature. 3. Since the initial accuracy for all devices is now specified as ± ...
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... Package Outline—12-Pin QFN Figure 22 illustrates the package details for the Si85xx. Table 14 lists the values for the dimensions shown in the illustration. Figure 22. 12-Pin QFN Package Diagram Table 14. QFN-12 Package Diagram Dimensions Dimension aaa bbb ccc ddd eee Notes: 1. All dimensions shown are in millimeters (mm). ...
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... Si85xx 8. Recommended PCB Landing Pattern (12-Pin QFN) Figure 23 illustrates the PCB land pattern details for the 12-pin QFN package. Table 15 lists the values for the dimensions shown in the illustration. Figure 23. 12-Pin QFN PCB Land Pattern Table 15. 12-Pin QFN PCB Land Pattern Dimensions ...
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... Circle Bottom-Left Justified YY = Year WW = Work Week Si85XX TTTTTT YYWW Figure 24. QFN Top Marking Table 16. Top Marking Explanation Si85XX: Where XX = 01, 02, 03, 11, 12, 13, 17, 18, 19 Manufacturing lot code Pin 1 Identifier Corresponds to the year and work week of the assembly build date. Preliminary Rev. 0.21 Si85xx 29 ...
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... Si85xx 10. Package Outline: Wide Body SOIC Figure 25 illustrates the package details for the wide-body SOIC package. Table 17 lists the values for the dimensions shown in the illustration. 30 Figure 25. 20-Pin Wide Body SOIC Preliminary Rev. 0.21 ...
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... Preliminary Rev. 0.21 Min Max — 2.65 0.10 0.30 2.05 — 0.31 0.51 0.20 0.33 12.80 BSC 10.30 BSC 7.50 BSC 1.27 BSC 0.40 1.27 0.25 0.75 0° 8° — 0.10 — 0.33 — 0.10 — 0.25 — 0.10 — 0.20 Si85xx 31 ...
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... Si85xx 11. Recommended PCB Landing Pattern (20-Pin SOIC) Figure 26 illustrates the PCB land pattern details for the 20-pin SOIC package. Table 18 lists the values for the dimensions shown in the illustration. Figure 26. 20-Pin SOIC PCB Land Pattern Table 18. 20-Pin SOIC PCB Land Pattern Dimensions ...
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... TW e3 Figure 27. SOIC Top Marking Table 19. Top Marking Explanation Si85XX-IS Where XX = 01, 02, 03, 11, 12, 13, 17, 18, 19 Assigned by the Assembly House. Corresponds to the year and work week of the mold date. Manufacturing lot code “e3” Pb-Free Symbol TW = Taiwan Preliminary Rev. 0.21 Si85xx 33 ...
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... Si85xx OCUMENT HANGE IST Revision 0.1 to Revision 0.2 Updated Table 1, “Electrical Specifications,” on page 4. Added 20-pin wide-body SOIC package option. Updated "6. Ordering Guide" on page 26. All devices are now specified to ±5% initial accuracy. All devices are now specified for operation over –40 to ...
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... N : OTES Preliminary Rev. 0.21 Si85xx 35 ...
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... Si85xx C I ONTACT NFORMATION Silicon Laboratories Inc. 400 West Cesar Chavez Austin, TX 78701 Tel: 1+(512) 416-8500 Fax: 1+(512) 416-9669 Toll Free: 1+(877) 444-3032 Please visit the Silicon Labs Technical Support web page: https://www.silabs.com/support/pages/contacttechnicalsupport.aspx and register to submit a technical support request. The information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice. ...