BMSKTOPASA900(DCE) Toshiba, BMSKTOPASA900(DCE) Datasheet
BMSKTOPASA900(DCE)
Specifications of BMSKTOPASA900(DCE)
Related parts for BMSKTOPASA900(DCE)
BMSKTOPASA900(DCE) Summary of contents
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... TOSHIBA Original RISC 32-Bit Microprocessor ARM Core Family TMPA900CMXBG TENTATIVE Rev.0.5 Semiconductor Company ...
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ARM, ARM Powered, AMBA, ADK, ARM9TDMI, TDMI, PrimeCell, RealView, Thumb, Cortex, Coresight, ARM9, ARM926EJ-S, Embedded Trace Macrocell, ETM, AHB, APB, and KEIL are registered trademarks or trademarks of ARM Limited in the EU and other countries. **************************************************************************************************************** TENTATIVE TMPA900CM- ...
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Introduction - Notes on the registers - This device has SFR (Special Function Register) each IP (Peripheral circuits). SFR is shown as following in this data book lists ・ IP lists show the register name, address and ...
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Overview and Features TMPA900CM is a 32-bit RISC microcontroller with a built-in ARM9 TMPA90xCMXBG is a 289-pin BGA package product. Features of the product are as follows: (1) ARM926EJ-S manufactured by ARM is used. • Data cache: 16 Kbytes ...
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UART: 3 channels • Channel 0: supports Full UART / supports IrDA1.0 mode. • Channel 1: supports TXD/RXD/U1CTSn 3 wires UART • Channel 2: supports TXD/RXD 2 wires UART (10) USB Device controller: 1 channel • Supports high communication ...
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Interrupt function: 28types • External 6types (14 pins): External Interrupt(edge: rise and fall, level: High and Low) • Internal : 22 types 16-bit timer × 3, RTC × 1, and A/D converter × 1 LCDC × 1, NANDFC × ...
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Operating voltage • Internal DVCC1A and DVCC1B = 1.5V ± 0.1V • High-frequency oscillator and power supply for PLL, DVCC1C = 1.5V ± 0.1V • External I/O DVCCM for memory = 3.0V to 3.6V or 1.8V ± 0.1V • ...
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TENTATIVE Data Cache 16Kbyte CPU Inst. LCD LCDC Controller (Bus Master3) LCD Data Process LCDDA Accelerator (Bus Master4) CPU Data Interrupt Controller I2S I/F (2ch) NANDF Controller (2ch) SD Host Controller (1ch) CPU Data Synchronous Serial Port (2ch) CMOS image ...
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Pin Configuration and Functions This section provides a TMPA900CM, names of I/O pins, and brief description of their functions. 2.1 Pin configuration diagram (Top View) Figure 2.1.1 shows the TMPA900CM pin configuration (Package: FBGA289-P-1515-0.80AZ) About the detail pin configuration, ...
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DVSSCOM DVCC1A SM3/XT2 DVCC3IO DVSSCOM PC2/PWE SP4/RTCK SP0/TCK DVSSCOM SP5/TDO SP2/TDI SP1/TMS PG0/ PG2/ SP3/ TRSTn SDC0DAT0 ...
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A A10 A11 A12 SE4/A4 SE3/A3 SE2/A2 B B10 B11 B12 SF2/A10 SF1/A9 SF0/A8 C C10 C11 C12 SF7/A15 SF6/A14 SF5/A13 D D10 D11 D12 SG3/A19 SG2/A18 SG1/A17 E E10 E11 E12 SG6/A22 SG5/A21 DVCCM F F10 ...
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PJ0/LD8 PJ1/LD9 PJ2/LD10 PJ4/LD12/ PJ5/LD13/ PJ6/LD14/ CMSPCK CMSHSY CMSHBK AVCC3AD VREFH VREFL PD0/AN0 PD1/AN1 PD2/AN2 PD3/AN3 PD4/AN4/ PD5/AN5 ...
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K K10 K11 DVSSCOM DVCCM SH7/DMCCSn L L10 L11 DVCC3IO DVSSCOM SH3/SMCCS0n M M10 M11 SN2/ SN1/ DVSSCOM SELJTAG SELDVCCM N N10 N11 PB3/KO3 PM3/ PM2/I2S1DATO I2S1MCLK P P10 P11 PB2/KO2 PB1/KO1/ PM1/I2S1CLK LCLAC R R10 R11 SN0/ PB0/KO0 PT2/SP0DO ...
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Pin Names and Functions The names and functions of I/O pins are shown below. Pins associated with memory are switched to either of two types of MPMC (MPMC0/1) depending on the status of the external pin “SELMEMC”. Table 2.2.1 ...
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Pin name Number of Input/Output pins − SJ3 DMCCASn 1 Output DMCCASn Output − SJ4 DMCBA0 1 Output DMCBA0 Output − SJ5 DMCBA1 1 Output DMCBA1 Output − SJ6 DMCCKE 1 Output DMCCKE Output − − SK0 DMCSDQM0 1 Output ...
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Pin name Number of pins Input/Output − SM0 1 X1 Input − SM1 1 X2 Output SM2 - 1 XT1 Input − SM3 1 XT2 Output − SM4 1 RESETn Input − − SM6 to SM7 2 AM0 to AM1 ...
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Pin name Number of pins Input/Output − SU0 1 LCLCP Output − SU1 1 LCLAC Output − − SU3 1 LCLFP Output − SU4 1 LCLLP Output Note: Pin names "SA0 through SA7, …, and SU0 through SU4" are symbols ...
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Pin name Number of pins Input/Output PA0 to PA3 Input KI0 to KI3 4 Input PB0 Output KO0 1 Output LCLCP PB1 Output 1 KO1 Output PB2 Output 1 KO2 Output PB03 Output 1 KO3 Output − PC2 Output PWE ...
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Table 2.2.1 Pin names and functions (6/8) Pin name Number of Input/Output pins PF6 Input/Output I2C1CL 1 Input/Output U2TXD Output PF7 Input/Output I2C1DA Input/Output INTC 1 Input U2RXD Input PG0 to PG3 Input/Output 4 SDC0DAT0 to Input/Output SDC0DAT3 PG4 Input/Output ...
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Table 2.2.1 Pin names and functions (7/8) Pin name Number of pins Input/Output PM0 Input/Output 1 I2S1WS Input/Output PM1 Input/Output 1 I2S1CLK Input/Output PM2 Input/Output 1 I2S1DATO Output PM3 Input/Output 1 I2S1MCLK Output PN0 Input/Output U0TXD 1 Output SIR0OUT Output ...
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Pin name Number of pins Input/Output PT4 Input/Output 1 U1TXD Output PT5 Input/Output 1 U1RXD Input PT6 Input/Output 1 U1CTSn Output PT7 Input/Output 1 X1USB Input PU0 to PU7 Input/Output NDD0 to NDD7 8 Input/ Output LD0~LD7 Output PV0 Input/Output ...
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Pin name Number of pins Power pins DVCC1A 8 Power supply DVCC1B 3 Power supply DVCC1C 2 Power supply DVSS1C 1 Power supply DVCC3IO 5 Power supply DVCCM 11 Power supply DVCC3LCD 3 Power supply AVCC3AD 1 Power supply AVSS3AD ...
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Pin Functions and Initial Values Arranged by Type of Power Supply - 1 (DVCCM ) Power supply Typical pin to be used name SA0 to SA7 SB0 to SB7 SC0 to SC7 SD0 to SD7 SE0 to SE7 SF0 to ...
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Pin Functions and Initial Values Arranged by Type of Power Supply – 2 (DVCCM) Power supply to Typical pin name be used SL0 SL1 DMCDCLKN SL2 - DVCCM SL4 DMCDDQS0 SL5 DMCDDQS1 SL6 - PR0 RESETOUTn PR1 PR2 Note 1: ...
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Pin Functions and Initial Values Arranged by Type of Power Supply – 3 (DVCC3IO) Power supply Typical pin name to be used SM2 SM3 SM4 - SM6 SM7 SN0 SN1 SELDVCCM SN2 SP0 SP1 SP2 SP3 SP4 SP5 PA0 to ...
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Pin Functions and Initial Values Arranged by Type of Power Supply – 4 (DVCC3IO) Power supply Alternative Typical pin name to be used PN0 PN1 PN2 PN3 PN4 PN5 PN6 PN7 PT0 PT1 PT2 PT3 DVCC3IO PT4 PT5 PT6 PT7 ...
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Pin Functions and Initial Values Arranged by Type of Power Supply – 7 (AVCC3AD) Power supply Typical pin name to be used PD0 PD1 PD2 PD3 AVCC3AD PD4 PD5 PD6 PD7 Note 1: Pin names "SA0 through SA7, …, and ...
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Pin Functions and Initial Values Arranged by Type of Power Supply – 8 (USB Device) Power supply Typical pin name to be used SR0 SR1 AVDD3C/T SR3 SR4 Note 1: Pin names "SA0 through SA7, …, and SU0 through SU4" ...
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Operational Description This chapter provides a brief description of the CPU circuitry of the TMPA900CM. 3.1 CPU This section describes the basic operations of the CPU of the TMPA900CM for each block. Note that this document provides only an ...
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Reset Operation Before resetting the TMPA900CM, make sure that the power supply voltage is within the operating range, oscillation from the internal oscillator is stable at 20 system clock cycles (0.8 μ MHz) at least, ...
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Exceptions The TMPA900CM includes 7 types of exception, and each of them has privileged processing mode. Exception Reset Undefined instruction execution Software interrupt (SWI) instruction Pre-fetch abort Data abort IRQ FIQ TENTATIVE Address 0x00000000 0x00000004 0x00000008 It is used ...
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Multilayer AHB The TMP900CM uses a multilayer AHB bus system with 7 layers. Data Cache 16Kbyte LCD Controller (Bus Master3) LCD Data Process Accelerator (Bus Master4) Interrupt Controller I2S I/F (2ch) NANDF Controller (2ch) SD Host Controller (1ch) Synchronous ...
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JTAG Interface 3.2.1 Overview The TMPA900CMXBG provides a boundary-scan interface that is compatible with Joint Test Action Group (JTAG) specifications and uses the industry-standard JTAG protocol (IEEE Standard 1149.1•1990 <Includes IEEE Standard 1449.1a•1993>). This chapter describes the JTAG interface, ...
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Signal Summary and Connection Example The JTAG interface signals are listed below. TDI JTAG serial data input ・ TDO JTAG serial data output ・ TMS JTAG test mode select ・ TCK JTAG serial clock input ・ TRSTn JTAG test ...
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What Is Boundary Scan? With the evolution of ever-denser integrated circuits (ICs), surface-mounted devices, double-sided component mounting on printed-circuit boards (PCBs), and set-in recesses, in-circuit tests that depend upon physical contact like the connection of the internal board and ...
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JTAG Controller and Registers The processor contains the following JTAG controller and registers: Instruction register Boundary scan register Bypass register Device identification register Test Access Port (TAP) controller JTAG basically operates to monitor the TMS input signal with the ...
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The bypass register is 1 bit wide. When the TAP controller is in the Shift-DR (bypass) state, the data on the TDI pin is shifted into the bypass register, and the bypass register output shifts to the date out on ...
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Boundary Scan Register The boundary scan register provides all the inputs and outputs of the TMPA900CM processor except some analog outputs and control signals. The pins of the TMPA900CM allow any pattern to be driven by scanning the data ...
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TAP Controller The processor incorporates the 16-state TAP controller stipulated in the IEEE JTAG specification. 3.2.9 Resetting the TAP Controller The TAP controller state machine can be put into the Reset state by the following method. Assertion of the ...
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TENTATIVE The following paragraphs describe each of the controller states. The left column in Figure 3.2.6 is the data column, and the right column is the instruction column. The data column and instruction column reference the data register (DR) and ...
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TENTATIVE • Shift-DR In this controller state, the test data register connected between TDI and TDO shifts data out serially. When the TAP controller is in this state, then it remains in the Shift-DR state if TMS is held low, ...
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TENTATIVE • Exit 1-IR This is a temporary controller state. When the TAP controller is in this state, it moves to either the Pause-IR state if TMS is held low, or the Update-IR state if TMS is held high. • ...
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Boundary Scan Order Table 3.2.2 shows the boundary scan order with respect to the processor signals. TDI → 1 (PC6)→ 2(PC7)→ …→180(PC4)→181(PC2)→TDO Table 3.2.2 JTAG Scan Order of the TMPA900CM Processor Pins Pin No. Name No. TDI 1 PC6 ...
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Instructions Supported by the JTAG Controller Cells This section describes the instructions supported by the JTAG controller cells of the TMPA900CM. (1) EXTEST instruction The EXTEST instruction is used for external interconnect tests. The EXTEST instruction permits BSR cells ...
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TENTATIVE (2) SAMPLE/PRELOAD instruction This instruction targets the boundary scan register between TDI and TDO. As its name implies, the SAMPLE/PRELOAD instruction provides two functions. SAMPLE allows the input and output pads monitored. While it ...
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BYPASS instruction This instruction targets the bypass register between JTDI and JTDO. The bypass register provides the shortest serial path that bypasses the IC (between JTDI and JTDO) when the test does not require control or monitoring of the ...
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Memory Map The memory map of TMPA900CM is as follows: Table 3.3.1 Outline of access to internal area Item CPU address width CPU data bus width Internal operation frequency Minimum bus cycle Internal RAM Internal Boot ROM Internal I/O ...
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Activation of the internal Start Address BOOT ROM 0x0000_0000 Internal ROM : 8KB+ 8KB 0x0000_2000 0x0000_4000 SMCCS0n 0x0100_0000 Unused area 0x2000_0000 Unused area 0x2100_0000 SMCCS0n 0x4000_0000 DMCCSn 0x6000_0000 SMCCS1n 0x8000_0000 Unused area 0xA000_0000 Unused area 0xC000_0000 Unused area 0xE000_0000 Unused ...
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Activation of the internal Address BOOT ROM 0x0000_0000 Internal ROM : 8KB+ 8KB 0x0000_2000 0x0000_4000 SMCCS0n 0x0100_0000 Unused area 0x2000_0000 Unused area 0x2100_0000 SMCCS0n 0x4000_0000 DMCCSn 0x6000_0000 SMCCS1n 0x8000_0000 Unused area 0xA000_0000 Unused area 0xC000_0000 Unused area 0xE000_0000 Unused area ...
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Start address End address 0xF000_0000 0xF000_0FFF 0xF001_0000 0xF001_0FFF 0xF002_0000 0xF002_0FFF 0xF003_0000 0xF003_0FFF 0xF004_0000 0xF004_0FFF 0xF004_1000 0xF004_1FFF Internal IO 0xF004_2000 0xF004_2FFF (APB) 0xF005_0000 0xF005_0FFF 1MB 0xF006_0000 0xF006_0FFF 0xF007_0000 0xF007_0FFF 0xF007_1000 0xF007_1FFF 0xF008_0000 0xF008_0FFF 0xF009_0000 0xF009_0FFF 0xF00A_0000 0xF00A_0FFF 0xF00B_0000 0xF00B_0FFF Internal IO ...
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Boot mode A few boot modes are available for choice to this microprocessor depending on the external pin setting. 1. Boot memory setting Mode setting pin RESETn AM1 AM0 External ...
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System Controller 3.4.1 Remapping function Using the remapping function, this LSI can access the 8K-byte area of the built-in RAM from two memory areas (0x0000_0000 to 0x0000_1FFF and 0xF800_2000 to 0xF800_3FFF). It turns on the Remapping function by writing ...
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BOOT mode 0x0000_0000 Internal ROM 16 KB 0x0000_2000 0x0000_4000 Unused area 0x2100_0000 External area 0xF000_0000 Internal IO area 0xF800_0000 Internal RAM-3: 0xF800_2000 8 KB (Remap) Internal RAM-0: 0xF800_4000 16 KB Internal RAM-1: 0xF800_8000 8 KB 0xF800_A000 Unused area 0xF801_0000 Unused ...
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Register Descriptions The system controller has the following register. Register Address Name (base+) Remap 0x0004 1. Remap Register Bit Bit Symbol − [31:1] [0] REMAP [Explanation] a. <REMAP> the register that enables the REMAP function. By writing ...
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Clock Controller 3.5.1 Overview The clock controller is a circuit that controls the clock for the overall MCU. It has the following features using a clock multiplication circuit (PLL), the clock controller supplies a clock of up ...
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Block Diagrams XT1 fs Low-frequency oscillator XT2 SYSCR3<PLLON>, <ND>, <C2S> SYSCR2<LUPFLAG> Lock-up timer (for PLL) Clock circuit (PLL) × High-frequency X1 oscillator f X2 OSCH 48/24MHz X1USB f FCLK ÷2 CLKCRn<ENIPx> CLKCRn<ENIPx> CLKCRn<ENIPy> CLKCRn<ENIPz> TENTATIVE Clock gear fc ...
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TENTATIVE Clock frequency input from the X1 and X2 pins is defined as f from the XT1 and XT2 pins is defined as f defined as clock f for the CPU core. For peripheral IPs connected to the AHB bus, ...
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Clock constraints are defined below. Select a clock that meets these criteria for intended applications. Table 3.5.1 Clock constraints @ 70°C (a) f OSCH (High speed oscillator frequency) (b) f PLL (PLL output frequency) (c) f ...
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The table below shows the examples of recommended uses that meet the criteria listed above. Table 3.5.3 Examples of recommended uses @ 0 to 70°C High speed oscillation: f OSCH (1) USB required, 24 MHz Maximum CPU: 192 MHz (2) ...
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Operation Descriptions 3.5.2.1 Register Descriptions The following lists the SFRs and their functions. Register Address Name (base+) SYSCR0 0x000 System Control Register 0 SYSCR1 0x004 System Control Register 1 SYSCR2 0x008 System Control Register 2 SYSCR3 0x00C System Control ...
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SYSCR0 (System Control Register 0) Bit Bit Type Symbol − − [31:6] [5] Reserved R/W − − [4] [3] Reserved R/W − − [2] [1] Reserved R/W − − [0] TENTATIVE Reset Value Undefined Read undefined. Write as zero. ...
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SYSCR1 (System Control Register 1) Bit Bit Type Symbol − − [31:3] [2:0] GEAR R/W [Description] a. <GEAR> Programs the clock gear. 0y000: fc 0y001: fc/2 0y010: fc/4 0y011: fc/8 0y1xx: Reserved TENTATIVE Reset Value Undefined Read undefined. Write ...
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SYSCR2 (System Control Register-2) Bit Bit Type Symbol − − [31:8] [7] Reserved R/W − − [6:2] [1] FCSEL R/W [0] LUPFLAG RO [Description] a. <FCSEL> Selects the clock to be output from the PLL. 0y0: f OSCH 0y1: ...
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SYSCR3 (System Control Register 3) Bit Bit Type Symbol − − [31:8] [7] PLLON R/W − − [6] [5] C2S R/W [4:0] ND R/W [Description] a. <PLLON> Controls the operation of the PLL. 0y0: OFF 0y1 <C2S> ...
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SYSCR4 (System Control Register 4) Bit Bit Type Symbol − − [31:8] [7:4] RS R/W [3:2] IS R/W [1:0] FS R/W [Description] a. <RS> PLL constant value setting 3 Program the following values according to PLL multiplying factor and ...
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SYSCR5 (System Control Register 5) Bit Bit Type Symbol − − [31:1] [0] PROTECT RO [Description] By setting a dual key to the SYSCR6 and SYSCR7 registers, protection (write operation to certain SFRs in the clock controller) can be ...
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SYSCR6 (System Control Register 6) Bit Bit Type Symbol − − [31:8] [7:0] P-CODE0 WO [Description] a. <P-CODE0> Used to set the protect code 0. (the value of 1st-KEY and 2nd-KEY) 8. SYSCR7 (System Control Register 7) Bit Bit ...
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CLKCR5 (Clock Control Register-5) Bit Bit Type Symbol − − [31:7] [6] Reserved R/W − − [5] [4] USBH_CLKEN R/W [3] Reserved R/W [2] R/W SEL_TIM45 [1] R/W SEL_TIM23 [0] SEL_TIM01 R/W [Description] a. < USBH_CLKEN > Clock selection ...
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System Clock Controller The system clock controller generates a clock to be supplied to the CPU core (f other built-in I/Os (f HCLK SYSCR1<GEAR2:0> to change the high speed clock gear 8-speed (fc, fc/2, ...
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PLL output: f PLL Lock-up timer <LUPFLAG> CPU clock f FCLK PLL operation and lock-up start Setting example – 2: PLL stop (SYSCR2) LUP: Dummy instruction execution (Note) (SYSCR3) <FCSEL> <PLLON> PLL output: f PLL CPU clock f ...
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Boot ROM TMPA900CM contains a boot ROM for loading a user program to the internal RAM. The following loading methods are supported. 3.6.1 Operation Modes TMPA900CM has two operation modes: external memory mode and internal boot ROM mode. Either ...
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Hardware Specifications of the Internal Boot ROM (1) Memory map Figure 3.6.1 shows a memory map of BOOT mode. The internal boot ROM consists ROM and is assigned to addresses from 0x0000_0000 to 0x0000_3FFF. Internal boot ...
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The boot ROM elimination function After the boot sequence is executed in BOOT mode, remapping is executed and the internal boot ROM area changes into RAM. BOOT mode 0x0000_0000 Internal ROM 16 KB 0x0000_2000 0x0000_4000 Unused area 0x2100_0000 External ...
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Outline of Boot Operation USB can be selected as the transfer source of boot operation. After reset, operation of the boot program on the internal boot ROM follows the flow chart shown in Figure 3.6.3. In any case, the ...
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Vector in ROM 0x0000 0000 BOOT ROM (16KB) ・ ・ Vector in RAM 0xF800 2000 User program LOAD area: vector area included (8KB) 0xF800 4000 User program LOAD area (16KB) 0xF800 8000 Boot program work space and stack space area ...
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Example of USB Boot In boot from USB, user program vector is downloaded to 8KB of Remap area (0xF800_2000 to 0xF800_3FFF), program is downloaded to 16KB of internal RAM area (0xF800_4000 to 0xF800_7FFF). Boot program remaps the area, and ...
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CPU status and port settings ARM926EJ-S starts in supervisor mode after reset, and the boot program executes all programs in supervisor mode without any mode changes. No port settings are required as ports used in the boot program are ...
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Download via USB (1) Connection example Figure 3.6.5 shows an example of USB connection (assuming that NOR Flash is program memory) PC USB Host Figure 3.6.5 USB connection example (2) Overview of the USB interface specifications Set the oscillation ...
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The following shows an overview of the USB communication flow. Host (PC) Send GET_DESCRIPTOR. Connection recognition Send DESCRIPTOR information. Data transfer Send a microcontroller information command. Convert Motorola S3 format data. Send microcontroller information data. Check data Send the user ...
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TENTATIVE The following shows the connection of Vendor class request. The table below shows the setup command data structure. Table 3.6.6 Setup Command Data Structure Field bmRequestType 0x40 bRequest 0x00, 0x02, 0x04 wValue 0x00~0xFFFF wIndex 0x00~0xFFFF wLength 0x0000 The table ...
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TENTATIVE The table below shows standard request commands. Table 3.6.8 Standard request commands Standard request GET_STATUS CLEAR_FEATURE SET_FEATURE SET_ADDRESS GET_DESCRIPTOR SET_DESCRIPTOR GET_CONFIGRATION SET_CONFIGRATION GET_INTERFACE SET_INTERFACE SYNCH_FRAME The table below shows information to be returned by GET_DESCRIPTOR. Table 3.6.9 Replies to ...
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TENTATIVE Configuration Descriptor Field bLength 0x09 bDescriptorType 0x02 wTotalLength 0x0020 bNumInterfaces 0x01 bConfigurationValue 0x01 iConfiguration 0x00 bmAttributes 0x80 MaxPower 0x31 Interface Descriptor Field bLength 0x09 bDescriptorType 0x04 bInterfaceNumber 0x00 bAlternateSetting 0x00 bNumEndpoints 0x02 bInterfaceClass 0xFF bInterfaceSubClass 0x00 bInterfaceProtocol 0x50 iIinterface ...
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TENTATIVE Endpoint Descriptor (When the USB host supports USB2.0) Field <Endpoint1> blength 0x07 bDescriptorType 0x05 bEndpointAddress 0x81 bmAttributes 0x02 wMaxPacketSize 0x0200 bInterval 0x00 <Endpoint2> bLength 0x07 bDescriptor 0x05 bEndpointAddress 0x02 bmAttributes 0x02 wMaxPacketSize 0x0200 bInterval 0x00 Endpoint Descriptor (When the ...
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The table below shows information replied to the microcontroller information command. Table 3.6.10 Information Replied to the Microcontroller Information Command Microcontroller information TMPA900CM 0x54,0x4D,0x50,0x41,0x39,0x30,0x30,0x43,0x4D,0x20,0x20,0x20,0x20,0x20,0x20 Note: produnct name in the Microcontroller information includes 6 spaces at the end of the product ...
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TENTATIVE (3) Description of the USB boot program operation The boot program transfers data in Motorola S3 format sent from the PC to the internal RAM. The user program starts operating after data transfer is completed. The start address of ...
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Usage Note Following are the note when use the BOOT ROM. 1．USB connector The USB connector must not be connected or disconnected during USB boot. 2. Software on the PC A dedicated USB device driver and application software installed ...
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Interrupts 3.7.1 Functional Overview • Supports 28 interrupt sources. • Assigns 32 levels of fixed hardware priorities to the interrupt sources (to be used if multiple interrupt requests of the same software priority level are made simultaneously). • Enables ...
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Logic circuit of Interrupt request VICIntEnable [31:0] VICINTSOURCE [31:0] VICSoftInt [31:0] TENTATIVE VICIntSelect [31:0] TMPA900CM- 87 TMPA900CM VICIRQStatus [31:0] VICFIQStatus [31:0] VICRawInterrupt [31:0] 2009-10-14 ...
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Operational Description For Interrupt Control, FIQ (Fast Interrupt Request) and IRQ (Interrupt Request) are available. The TMPA900CM only has one FIQ source. FIQ is a low- latency interrupt and has the highest priority level. In handling FIQ, Interrupt Service ...
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Interrupt vector flowchart An interrupt occurs VIC checks if the interrupt is FIQ ? NO CPU branches to 0x00000018 (& disable interrupts) Branches to IRQ interrupt processing Read the VICADDRESS register and Branch to the interrupt vector Save register ...
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Operation Timing for Nested Interrupts 1) Interrupt priority: INTS[1] ≥ INTS[2] INTS[1] (High Active) INTS[2] (High Active) Internal nVICIRQ (Low Active) Note 1: When the VICADDRESS register is read, interrupts having priority level equal to or lower than the ...
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Interrupt Sources Interrupt source number (Note) 0 WDT 1 RTC 2 Timer01 3 Timer23 4 Timer45 5 GPIOD:INTA (TSI), INTB ch0 ch1 8 ADC 9 UART ch2 10 UART ch0 11 ...
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SFRs The following lists the SFRs: Register Address Name (base+) VICIRQSTATUS 0x0000 VICFIQSTATUS 0x0004 VICRAWINTR 0x0008 VICINTSELECT 0x000C VICINTENABLE 0x0010 VICINTENCLEAR 0x0014 VICSOFTINT 0x0018 VICSOFTINTCLEAR 0x001C VICPROTECTION 0x0020 VICSWPRIORITYMASK 0x0024 − 0x0028 VICVECTADDR0 0x0100 VICVECTADDR1 0x0104 VICVECTADDR2 0x0108 VICVECTADDR3 ...
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Register Address Name (base+) VICVECTPRIORITY4 0x0210 VICVECTPRIORITY5 0x0214 VICVECTPRIORITY6 0x0218 VICVECTPRIORITY7 0x021C VICVECTPRIORITY8 0x0220 VICVECTPRIORITY9 0x0224 VICVECTPRIORITY10 0x0228 VICVECTPRIORITY11 0x022C VICVECTPRIORITY12 0x0230 VICVECTPRIORITY13 0x0234 VICVECTPRIORITY14 0x0238 VICVECTPRIORITY15 0x023C VICVECTPRIORITY16 0x0240 VICVECTPRIORITY17 0x0244 VICVECTPRIORITY18 0x0248 − 0x024C VICVECTPRIORITY20 0x0250 VICVECTPRIORITY21 0x0254 ...
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VICIRQSTATUS (IRQ Status Register) Bit Bit Symbol [31:0] IRQStatus [Description] a. <IRQStatus> IRQStatus [31:0] correspond to interrupt numbers respectively. Example: When bit 0 of this register is set WDT interrupt (interrupt source number ...
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VICINTSELECT (Interrupt Select Register) Bit Bit Symbol [31:0] IntSelect [Description] a. <IntSelect> IntSelect [31:0] correspond to interrupt source numbers respectively. Example: When bit 0 of this register is set to 1, the WDT interrupt (interrupt source ...
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VICINTENCLEAR (Interrupt Enable Clear Register) Bit Bit Symbol [31:0] IntEnable Clear [Description] a. <IntEnable Clear> IntEnable Clear [31:0] corresponds to interrupt source numbers respectively. Setting each bit in this register clears the setting of the corresponding ...
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VICSOFTINTCLEAR (Software Interrupt Clear Register) Bit Bit Symbol [31:0] SoftIntClear [Description] a. <SoftIntClear> SoftIntClear [31:0] correspond to interrupt source numbers respectively. Setting each bit in this register disables the corresponding software interrupt in the VICSOFTINT register. ...
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VICVECTADDR0 (Vector Address 0 Register) Bit Bit Symbol [31:0] VectorAddr 0 [Description] a. <VectorAddr 0> Before changing the setting of this register, be sure to disable the relevant interrupts. • VICVECTADDRn (Vector Address n Register)( 18, ...
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VICVECTPRIORITY0 (Vector Priority 0 Register) Bit Bit Symbol − [31:4] [3:0] VectPriority [Description] a. <VectPriority> If multiple interrupt requests of the same software priority level occur simultaneously, the hardware priority is used to determine the interrupt to be generated. ...
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DMAC (DMA Controller) 3.8.1 Functional Overview The DMA controller has the following features: Item Number of channels 8 ch DMA start Hardware request Software request 32 bits × 2 (AHB) Bus master Priority DMA channel 0 (high) to DMA ...
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DMA Transfer Types DMA Request DMA Transfer Direction Generator Memory-to-Peripheral Peripheral 1 Peripheral-to-Memory Peripheral 2 Memory-to-Memory DMAC 3 Peripheral-to-Peripheral Source peripheral Destination 4 peripheral Note 1: Peripheral that can use the single request: UART and LCDDA. Note 2: Recommendation: ...
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Memory-to-Memory Memory 4. Peripheral-to-peripheral 1) Integral multiple of the burst size DMACBREQ Source Peripheral DMACCLR AMBA Bus 2) Single transfer Source DMACSREQ Peripheral DMACCLR AMBA Bus 3) Not Integral Multiple of the burst size DMACBREQ Source DMACSREQ Peripheral DMACCLR ...
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Block Diagram − [15] LCDDA [14] SSP1 receive [13] SSP1 transmit [12] I2S1 [11] I2S0 [10] CPU Data. SD buf read [9] SD buf write [8] UART2 receive [7] UART2 transmit [6] CMSIF [5] NANDC [4] burst request SSP0 ...
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Register descriptions The following lists the SFRs: Address Register Name (base+) DMACIntStaus 0x0000 DMACIntTCStatus 0x0004 DMACIntTCClear 0x0008 DMACIntErrorStatus 0x000C DMACIntErrClr 0x0010 DMACRawIntTCStatus 0x0014 DMACRawIntErrorStatus 0x018 DMACEnbldChns 0x01C DMACSoftBReq 0x020 DMACSoftSReq 0x024 − 0x028 − 0x02C DMACConfiguration 0x030 − 0x034 ...
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Address Register Name (base+) DMACC6SrcAddr 0x1C0 DMACC6DestAddr 0x1C4 DMACC6LLI 0x1C8 DMACC6Control 0x1CC DMACC6Configuration 0x1D0 DMACC7SrcAddr 0x1E0 DMACC7DestAddr 0x1E4 DMACC7LLI 0x1E8 DMACC7Control 0x1EC DMACC7Configuration 0x1F0 − 0xFE0 − 0xFE4 − 0xFE8 − 0xFEC − 0xFF0 − 0xFF4 − 0xFF8 − 0xFFC ...
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DMACIntStatus (DMAC Interrupt Status Register) Bit Bit Symbol − [31:8] [7] IntStatus7 [6] IntStatus6 [5] IntStatus5 [4] IntStatus4 [3] IntStatus3 [2] IntStatus2 [1] IntStatus1 [0] IntStatus0 [Description] a. <IntStatus[7:0]> Indicates the status of the DMAC interrupt after reflecting the ...
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DMACIntTCStatus (DMAC Interrupt Terminal Count Status Register) Bit Bit Symbol − [31:8] [7] IntStatusTC7 [6] IntStatusTC6 [5] IntStatusTC5 [4] IntStatusTC4 [3] IntStatusTC3 [2] IntStatusTC2 [1] IntStatusTC1 [0] IntStatusTC0 [Description] a. <IntStatusTC[7:0]> Indicates the enabled state of the terminal count ...
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DMACIntTCClear (DMAC Interrupt Terminal Count Clear Register) Bit Bit Symbol − [31:8] [7] IntTCClear7 [6] IntTCClear6 [5] IntTCClear5 [4] IntTCClear4 [3] IntTCClear3 [2] IntTCClear2 [1] IntTCClear1 [0] IntTCClear0 [Description] a. <IntTCClear[7:0]> Writing 1 to each bit of this register ...
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DMACIntErrorStatus (DMAC Interrupt Error Status Register) Bit Bit Symbol − [31:8] [7] IntErrStatus7 [6] IntErrStatus6 [5] IntErrStatus5 [4] IntErrStatus4 [3] IntErrStatus3 [2] IntErrStatus2 [1] IntErrStatus1 [0] IntErrStatus0 [Description] a. <IntErrStatus[7:0]> Indicates the enabled state of the Error interrupt. TENTATIVE ...
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DMACIntErrClr (DMAC Interrupt Error Clear Register) Bit Bit Symbol − [31:8] [7] IntErrClr7 [6] IntErrClr6 [5] IntErrClr5 [4] IntErrClr4 [3] IntErrClr3 [2] IntErrClr2 [1] IntErrClr1 [0] IntErrClr0 [Description] a. <IntErrClr[7:0]> 0y1: Clear Error interrupt request. TENTATIVE Reset Type Value ...
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DMACRawIntTCStatus (DMAC Raw Interrupt Terminal Count Status Register) Bit Bit Symbol − [31:8] [7] RawIntTCS7 [6] RawIntTCS6 [5] RawIntTCS5 [4] RawIntTCS4 [3] RawIntTCS3 [2] RawIntTCS2 [1] RawIntTCS1 [0] RawIntTCS0 [Description] a. <RawIntTCS[7:0]> Indicates the Raw state of the terminal ...
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DMACRawIntErrorStatus (DMAC Raw Error Interrupt Status Register) Bit Bit Symbol − [31:8] [7] RawIntErrS7 [6] RawIntErrS6 [5] RawIntErrS5 [4] RawIntErrS4 [3] RawIntErrS3 [2] RawIntErrS2 [1] RawIntErrS1 [0] RawIntErrS0 [Description] a. <RawIntErrS[7:0]> Indicates the Raw state of the Error interrupt. ...
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DMACEnbldChns (DMAC Enabled Channel Register) Bit Bit Symbol − [31:8] [7] EnabledCH7 [6] EnabledCH6 [5] EnabledCH5 [4] EnabledCH4 [3] EnabledCH3 [2] EnabledCH2 [1] EnabledCH1 [0] EnabledCH0 [Description] a. <EnabledCH[7:0]> 0y0: Applicable channel bit is cleared when DMA transfer has ...
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DMACSoftBReq (DMAC Software Burst Request Register) Bit Bit Symbol − [31:15] [14] SoftBReq14 [13] SoftBReq13 [12] SoftBReq12 [11] SoftBReq11 [10] SoftBReq10 [9] SoftBReq9 [8] SoftBReq8 [7] SoftBReq7 [6] SoftBReq6 [5] SoftBReq5 [4] SoftBReq4 [3] SoftBReq3 [2] SoftBReq2 [1] SoftBReq1 ...
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DMACSoftSReq (DMAC Software Single Request Register ) Bit Bit Symbol − [31:16] − [15] [14] SoftSReq14 [13] SoftSReq13 [12] SoftSReq12 − [11:8] [7] SoftBReq7 [6] SoftBReq6 − [5:4] [3] SoftSReq3 [2] SoftSReq2 [1] SoftSReq1 [0] SoftSReq0 [Description] a. <SoftSReq[14:0]> ...
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DMACConfiguration (DMAC Configuration Register) Bit Bit Symbol − [31:3] [2] M2 [1] M1 [0] E [Description] a. <E> Write/read operation can be executed to any of the DMAC registers only when the DMA circuit is avtive. To perform DMA ...
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DMACC0SrcAddr (DMAC Channel0 Source Address Register) Bit Bit Symbol [31:0] SrcAddr [Description] a. <SrcAddr> Software configures each register directly before the channel is enabled. When the DMAchannel is enabled, the register is updated as the destination address is incremented ...
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DMACC0DestAddr (DMAC Channel0 Destination Address Register) Bit Bit Symbol [31:0] DestAddr [Description] a. <DestAddr> When transfer is taking place, don’t update this register. If you want to change the channel configuration, you must disable the channel first with the ...
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DMACC0LLI (DMAC Channel0 Linked List Item Register) Bit Bit Symbol [31:2] LLI − [1] [0] LM [Description] a. <LLI> The value set to <LLI> must be within 0xFFFF_FFF0. If the LLI is 0, then the current LLI is the ...
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DMACC0Control (DMAC Channel0 Control Register) Bit Bit Symbol [31] I [30] Prot[3] [29] Prot[2] [28] Prot[1] [27] DI [26] SI [25] D [24] S [23:21] Dwidth[2:0] [20:18] Swidth[2:0] [17:15] DBSize[2:0] [14:12] SBSize[2:0] [11:0] TransferSize TENTATIVE Reset Type Value Terminal ...
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The transfer source bit width must be an integral multiple of the transfer destination bit width. b. <DBSize[2:0]> Note: The burst size set in DBsize is unrelated to HBURST of the AHB bus. c. <SBSize[2:0]> Note: The ...
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DMACC0Configuration (DMAC Channel0 Configuration Register) Bit Bit Symbol − [31:19] [18] Halt [17] Active [16] Lock [15] ITC [14] IE [13:11] FlowCntrl − [10] [9:6] DestPeripheral − [5] [4:1] SrcPeripheral [0] E Note: Please refer to Table 3.8.2 DMA ...
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This is a DMA request peripheral number in binary. This setting will be ignored if memory is specified as the transfer destination. c. <SrcPeripheral> This is a DMA request peripheral number in binary. This setting will be ignored ...
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Special Function 1) Scatter/gather function When a part of image data is cut off and transferred, the image data is not be handled as consecutive data. The addresses of the image data to be transferred are scattered according to ...
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TENTATIVE 2) Linked list operation To use the scatter/gather function, a series of linked lists should be created to define source and destination data areas. LLI enables to transfer unordered multiple blocks sequentially. Each LLI transfers data based on the ...
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Example: When transferring data in the area enclosed by the square 0x00200 0x0A000 0x0B000 0x0C000 DMACCxSrcAddr: 0x0A200 DMACCxDestAddr: Destination address 1 DMACCxLLI: 0x200000 DMACCxControl: Set the number of burst transfers, etc. Linked List 0x0B200(SrcAddr) 0x200000 Dest Addr2 +4 0x200010 +8 ...
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Port Functions The list of the port pin functions and input-output port programming show how to configure each pin. Information on power sources is also provided as different power sources are used for individual external pins. Table 3.9.1 TMPA900CM ...
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TENTATIVE Table 3.9.2 TMPA900CM pin assignment (dual-purpose pins) TMPA900CM-128 TMPA900CM 2009-10-14 ...
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TENTATIVE Table 3.9.3 TMPA900CM address and initial value table TMPA900CM-129 TMPA900CM 2009-10-14 ...
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Data Registers [Notes on data registers] All data registers allow all the 8 bits to be read or written simultaneously also possible to mask certain bits in reading from or writing to the data registers. Data registers ...
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Port Function Settings This section describes the settings of Port A through Port V that can also function as general-purpose ports. Each port should basically be accessed in word (32-bit) units. 3.9.2.1 Port A Port A can be used ...
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GPIOADATA (Port A Data Register) Bit Bit Symbol − − [31:4] [3:0] PA[3:0] RO [Description] a. <PA[3:0]> Data register: Stores data. See notes on data registers for the bit mask function. 2. GPIOAIS (Port A Interrupt Select Register (Level ...
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GPIOAIBE (Port A Interrupt Select Register (Single edge and Both edge)) Bit Bit Symbol − [31:4] [3:0] PA3IBE to A0IBE [Description] a. <PA3IBE to PA0IBE> Interrupt both-edge register: Selects single edge or both-edge. 0y0: Single edge 0y1: Both-edge 4. ...
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GPIOARIS (Port A Interrupt Status Register (Raw)) Bit Bit Symbol − [31:4] [3:0] PA3RIS to PA0RIS [Description] a. <PA3RIS to PA0RIS> Interrupt raw status register: Monitors the interrupt status before being masked by the interrupt enable register. 0y0: Not ...
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Port B Port B can be used not only as general-purpose output pins but also as key output pins. By enabling open-drain output, Port B is used as key output (KO3-KO0). General-Purpose Output Setting Function Data Value GPIOBDATA General-purpose ...
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GPIOBDATA (Port B Data Register) Bit Bit Symbol − − [31:4] [3:0] PB[3:0] R/W [Description] a. <PB[3:0]> Data register: Stores data. See notes on data registers for bit masking. 2. GPIOBODE (Port B Open-drain Output Enable Register) Bit Bit ...
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Port C The upper 2 bits (bits [7:6]) of Port C can be used as general-purpose input/output pins and the lower 3 bits (bits [4:2]) can be used as general-purpose output pins. Port C can also be used as ...
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I C setting Function Data Value GPIOCDATA Bit 7 Bit 6 Bit 5 I2C0DA I2C0CL MLDALM setting Function Data Value GPIOCDATA MLDALM * Bit 7 Bit 6 Bit 5 USBOCn, USBPON, PWM output setting Function ...
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TENTATIVE Note: about PC2 setting This MCU implements power management circuity that can cut off power supply to circuit blocks other than some special circuits and I/O pins. For details, please refer to PMC chapter). Even if the power of ...
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Register Address Name (base+) GPIOCDATA 0x03FC GPIOCDIR 0x0400 GPIOCFR1 0x0424 GPIOCFR2 0x0428 GPIOCIS 0x0804 GPIOCIBE 0x0808 GPIOCIEV 0x080C GPIOCIE 0x0810 GPIOCRIS 0x0814 GPIOCMIS 0x0818 GPIOCIC 0x081C GPIOCODE 0x0C00 1. GPIOCDATA (Port C Data Register) Bit Bit Symbol − − [31:8] ...
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GPIOCDIR (Port C Data Direction Register) Bit Bit Symbol − [31:8] [7:6] PC7C to PC6C − [5] [4:2] PC4C to PC0C − [1:0] [Description] a. <PC7C to PC6C> Data direction register: Selects input or output when Port C is ...
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GPIOCFR2 (Port C Function Register 2) Bit Bit Symbol − [31:8] [7:6] PC7F2 to PC6F2 [5] Reserved [4:3] PC4F2 to PC3F2 [2:0] Reserved [Description] a. <PC7F2, PC6F2, PC4F2 to PC3F2> Function register 2: Controls the function setting. Note: 1 ...
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GPIOCIBE (Port C Interrupt Select Register (Single edge and Both edge)) Bit Bit Symbol − [31:8] [7] PC7IBE − [6:0] [Description] a. <PC7IBE> Interrupt both-edge register: Selects the trigger mode from single edge and both-edge. 0y0: Single edge 0y1: ...
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GPIOCIE (Port C Interrupt Enable Register) Bit Bit Symbol − [31:8] [7] PC7IE [6:0] Reserved [Description] a. <PC7IE> Interrupt enable register: Enables or disables interrupts. 0y0: Disabled 0y1: Enabled 9. GPIOCRIS (Port C Interrupt Status Register (Raw)) Bit Bit ...
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GPIOCMIS (Port C Interrupt Status Register (Masked)) Bit Bit Symbol − [31:8] [7] PC7MIS − [6:0] [Description] a. <PC7MIS> Masked interrupt status register: Monitors the interrupt status after being masked by the interrupt enable. 0y0: Not requested 0y1: Requested ...
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Following table is an example configurations of interrupt register. The configurations of each register and bit are shown below. Table 3.9.5 An example configurations of interrupt register (GPOxIS, GPIOxIBE, GPIOxIEV, GPIOxIE, GPIOxRIS, GPIOxMIS ...
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GPIOCIC (Port C Interrupt Clear Register) Bit Bit Symbol − [31:8] [7] PC7IC − [6:0] [Description] a. <PC7IC> Interrupt clear register: Clears edge-sensitive interrupts. 0y0: Invalid 0y1: Request cleared 12. GPIOCODE (Port C Open-drain Output Enable Register) Bit Bit ...
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Port D Port D can be used as general-purpose input. Port D can also be used as interrupt (INTB, INTA), ADC (AN7-AN0), and touch screen control (PX, PY, MX, MY) pins. General-purpose input and Interrupt settings Function Data Value ...
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Register Address Name (base+) GPIODDATA 0x03FC GPIODFR1 0x0424 GPIODFR2 0x0428 GPIODIS 0x0804 GPIODIBE 0x0808 GPIODIEV 0x080C GPIODIE 0x0810 GPIODRIS 0x0814 GPIODMIS 0x0818 GPIODIC 0x081C 1. GPIODDATA (Port D Data Register) Bit Bit Symbol − − [31:8] [7:0] PD[7:0] RO [Description] ...
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GPIODFR1 (Port D Function Register 1) Bit Bit Symbol − [31:8] [7:0] PD7F1 to PD0F1 [Description] a. <PD7F1 to PD0F1> Function register 1: Controls the function setting. 3. GPIODFR2 (Port D Function Register 2) Bit Bit Symbol − [31:8] ...
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GPIODIS (Port D Interrupt Select Register (Level and Edge)) Bit Bit Symbol − [31:8] [7:6] PD7IS to PD6IS [5:0] Reserved • [Description] a. <PD7IS to PD6IS> Interrupt sensitivity register: Selects the interrupt trigger mode from edge-sensitive and level-sensitive. 0y0: ...
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GPIODIEV (Port D Interrupt Select Register (“Falling edge/Low level” and “Rising edge/High level”)) Bit Bit Symbol − [31:8] [7:6] PD7IEV to PD6IEV [5:0] Reserved [Description] a. <PD7IEV to PD6IEV> Interrupt event register: Selects falling edge or rising edge for ...
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GPIODRIS (Port D Interrupt Status Register (Raw)) Bit Bit Symbol − [31:8] [7:6] PD7RIS to PD6RIS − [5:0] [Description] a. <PD7RIS to PD6RIS> Interrupt raw status register: Monitors the interrupt status before being masked by the interrupt enable register. ...
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GPIODIC (Port D Interrupt Clear Register) Bit Bit Symbol − [31:8] [7:6] PD7IC to PD6IC − [5:0] [Description] a. <PD7IC to PD6IC> Interrupt clear register: Clears edge-sensitive interrupts. 0y0: Invalid 0y1: Request cleared TENTATIVE Reset Type Value − Undefined ...
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Port F The upper 2 bits (bits [7:6]) of Port F can be used as general-purpose input/output pins. Port F can also be used as interrupt (INTC), UART (U2RXD, U2TXD) and I I2C1CL) pins. General-purpose Input and Interrupt settings ...
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Register Address Name (base+) GPIOFDATA 0x03FC GPIOFDIR 0x0400 GPIOFFR1 0x0424 GPIOFFR2 0x0428 GPIOFIS 0x0804 GPIOFIBE 0x0808 GPIOFIEV 0x080C GPIOFIE 0x0810 GPIOFRIS 0x0814 GPIOFMIS 0x0818 GPIOFIC 0x081C GPIOFODE 0x0C00 1. GPIOFDATA (Port F Data Register) Bit Bit Symbol − − [31:8] ...
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GPIOFFR1 (Port F Function Register 1) Bit Bit Symbol − [31:8] [7:6] PF7F1 to PF6F1 − [5:0] [Description] a. <PF7F1 to PF6F1> Function register 1: Controls the function setting. 4. GPIOFFR2 (Port Function Register2) Bit Bit Symbol − [31:8] ...
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GPIOFIBE (Port F Interrupt Select Register (Single edge and Both edge)) Bit Bit Symbol − [31:8] [7] PF7IBE − [6:0] [Description] a. <PFF7IBE> Interrupt both-edge register: Selects the trigger edge from single edge and both-edge. 0y0: Single edge 0y1: ...
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GPIOFIE (Port F Interrupt Enable Register) Bit Bit Symbol − [31:8] [7] PF7IE [6:0] Reserved [Description] a. <PF7IE> Interrupt enable register: Enables or disables interrupts. 0y0: Disabled 0y1: Enabled 9. GPIOFRIS (Port F Interrupt Status Register (Raw)) Bit Bit ...
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GPIOFMIS (Port F Interrupt Status Register (Masked)) Bit Bit Symbol − [31:8] [7] PF7MIS − [6:0] [Description] a. <PF7MIS> Masked interrupt status register: Monitors the interrupt status after being masked by the interrupt register. 0y0: Not requested 0y1: Requested ...
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GPIOFODE (Port F Open-drain Output Enable Register) Bit Bit Symbol − [31:8] [7:6] PF7ODE to PF6ODE − [5:0] [Description] a. <PF7ODE to PF6ODE> Open-drain output enable register: Selects the output mode from Push-Pull output and Open-drain output. 0y0: Push-Pull ...
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Port G Port G can be used as general-purpose input/output pins. Port G can also be used as SD host controller function pins (SDC0CLK, SDC0CD, SDC0WP, SDC0CMD, SDC0DAT3, SDC0DAT2, SDC0DAT1 and SDC0DAT0). General-purpuse input setting Function Data Value GPIOGDATA ...
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GPIOGDATA (Port G Data Register) Bit Bit Symbol − − [31:8] [7:0] PG[7:0] R/W [Description] a. <PG[7:0]> Data register: Stores data. See notes on data registers for the bit mask function. 2. GPIOGDIR (Port G Data Direction Register) Bit ...
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Port J Port J can be used as general-purpose input/output pins. Port J can also be used as LCD cotroller function pins (LD15-LD8) and CMOS image sensor control (CMSVSY, CMSHBK, CMSHSY and CMSPCK) pins. General-purpuse input setting Function Data ...
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GPIOJDATA (Port J Data Register) Bit Bit Symbol − − [31:8] [7:0] PJ[7:0] R/W [Description] a. <PJ[7:0]> Data Register: Stores data. See notes on data registers for the bit mask function. 2. GPIOJDIR (Port J Data Direction Register) Bit ...
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GPIOJFR2 (Port J Function Register2) Bit Bit Symbol − [31:8] [7:4] PJ7F2 to PJ4F2 − [3:0] [Description] a. <PJ7F2 to PJ0F2> Functin register 2: Controls the function setting. TENTATIVE Reset Type Value − Undefined Read as undefined. Write as ...
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Port K Port K can be used as general-purpose input/output pins. Port K can also be used as LCD controller function pins (LD23 to LD16) and CMOS image sensor control (CMSD7 toCMSD0) pins. General-purpuse input setting Function Data Value ...
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GPIOKDATA (Port K Data Register) Bit Bit Symbol − − [31:8] [7:0] PK[7:0] R/W [Description] a. <PK[7:0]> Data register: Stores data. See notes on data registers for the bit mask function. 2. GPIOKDIR (Port K Data Direction Register) Bit ...
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GPIOKFR2 (Port K Function Register2) Bit Bit Symbol − [31:8] [7:0] PK7F2 to PK0F2 [Description] a. <PK7F1 to PK0F1> Function register 1: Controls the function setting. TENTATIVE Reset Type Value − Undefined Read as undefined. Write as zero. R/W ...
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Port L Port L can be used as general-purpose input/output pins. (Bits [7:5] are not used.) In addition, Port L can also be used as I I2S0CLK and I2S0WS) and SPI function (SP1DI, SP1DO, SP1CLK and SP1FSS) pins. General-purpose ...
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Register Address Name (base+) GPIOLDATA 0x03FC GPIOLDIR 0x0400 GPIOLFR1 0x0424 GPIOLFR2 0x0428 1. GPIOLDATA (Port L Data Register) Bit Bit Symbol − − [31:8] − − [7:5] [4:0] PL[4:0] R/W [Description] a. <PL[4:0]> Data register: Stores data. See notes on ...
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GPIOLFR1 (Port L Function Register 1) Bit Bit Symbol − [31:8] − [7:5] [4:0] PL4F1 to PL0F1 [Description] a. <PL4F1 to PL0F1> Function register 1: Controls the function setting. 4. GPIOLFR2 (Port L Function Register 2) Bit Bit Symbol ...
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Port M Port M can be used as general-purpose input/output pins. (Bits [7:4] are not used.) Port M can also be used as I I2S1WS). General-purpose input setting Function Data Value GPIOMDATA General-purpose input * Bit 7 Bit 6 ...
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GPIOMDATA (Port M Data Register) Bit Bit Symbol − − [31:8] − − [7:4] [3:0] PM[3:0] R/W [Description] a. <PM[3:0]> Data register: Stores data. See notes on data registers for the bit mask function. 2. GPIOMDIR (Port M Data ...
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Port N Port N can be used as general-purpose input/output pins. Port N can also be used as UART/IrDA function (U0RTSn, U0DTRn, U0RIn, U0DSRn, U0DCDn, U0CTSn, U0RXD, U0TXD, SIR0IN, SIR0OUT) and interrupt function (INTD, INTE, INTF, INTG) pins. General-purpose ...
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Register Address Name (base+) GPIONDATA 0x03FC GPIONDIR 0x0400 GPIONFR1 0x0424 GPIONFR2 0x0428 GPIONIS 0x0804 GPIONIBE 0x0808 GPIONIEV 0x080C GPIONIE 0x0810 GPIONRIS 0x0814 GPIONMIS 0x0818 GPIONIC 0x081C 1. GPIONDATA (Port N Data Register) Bit Bit Symbol − − [31:8] [7:0] PN[7:0] ...
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GPIONFR1 (Port N Function Register 1) Bit Bit Symbol − [31:8] [7:2] PN7F1 to PN2F1 [1] Reserved [0] PN0F1 [Description] a. <PN7F1 to PN2F1,PN0F1> Function register 1: Controls the function setting. 4. GPIONFR2 (Port N Function Register 2) Bit ...
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GPIONIS (Port N Interrupt Select Register (Level and Edge)) Bit Bit Symbol − [31:8] [7:4] PN7IS to PN4IS [3:0] Reserved [Description] a. <PN7IS to PN4IS> Interrupt sensitivity register: Selects edge-sensitive or level-sensitive. 0y0: Edge-sensitive 0y1: Level-sensitive 6. GPIONIBE (Port ...
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GPIONIEV (Port N Interrupt Select Register(“Falling edge/Low level” and “Rising edge/High level”)) Bit Bit Symbol − [31:8] [7:4] PN7IEV to PN4IEV [3:0] Reserved [Description] a. <PN7IEV to PN4IEV> Interrupt event register: Selects falling edge or rising edge for edge-sensitive ...
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GPIONRIS (Port N Interrupt Status Register (Raw)) Bit Bit Symbol − [31:8] [7:4] PN7RIS to PN4RIS − [3:0] [Description] a. <PN7RIS to PN4RIS> Interrupt raw status register: Monitors the interrupt status before being masked by the interrupt enable register. ...
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GPIONIC (Port N Interrupt Clear Register) Bit Bit Symbol − [31:8] [7:4] PN7IC to PN4IC − [3:0] [Description] a. <PN7IC to PN4IC> Interrupt clear register: Clears edge-sensitive interrupts. 0y0: Invalid 0y1: Clear TENTATIVE Reset Type Value − Undefined Read ...
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Port R Bit 2 of Port R can be used as a general-purpose input/output pin and bits [1:0] can be used as general-purpose output pins. (Bits [7:3] are not used.) Port R can also be used as reset output ...
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Register Address Name (base+) GPIORDATA 0x03FC GPIORDIR 0x0400 GPIORFR1 0x0424 GPIORFR2 0x0428 GPIORIS 0x0804 GPIORIBE 0x0808 GPIORIEV 0x080C GPIORIE 0x0810 GPIORRIS 0x0814 GPIORMIS 0x0818 GPIORIC 0x081C 1. GPIORDATA (Port R Data Register) Bit Bit Symbol − − [31:8] − − ...
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GPIORFR1 (Port R Function Register 1) Bit Bit Symbol − [31:8] − [7:3] [2] Reserved [1] PR1F1 [0] PR0F1 [Description] a. <PR0F1 to PR1F1> Function register 1: Controls the function setting. 4. GPIORFR2 (Port R Function Register 2) Bit ...
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GPIORIS (Port R Interrupt Select Register (Level and Edge)) Bit Bit Symbol − [31:8] − [7:3] [2] PR2IS [1:0] Reserved [Description] a. <PR2IS> Interrupt sensitivity register: Selects edge-sensitive or level-sensitive. 0y0: Edge-sensitive 0y1: Level-sensitive 6. GPIORIBE (Port R Interrupt ...
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GPIORIEV (Port R Interrupt Select Register(“Falling edge/Low level” and “Rising edge/High level”)) Bit Bit Symbol − [31:8] − [7:3] [2] PR2IEV [1:0] Reserved [Description] a. <PR2IEV> Interrupt event register: Selects falling edge or rising edge for edge-sensitive interrupts, and ...
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GPIORRIS (Port R Interrupt Status Register (Raw)) Bit Bit Symbol − [31:8] − [7:3] [2] PR2RIS − [1:0] [Description] a. <PR2RIS> Interrupt raw status register: Monitors the interrupt status before masking. 0y0: Not requested 0y1: Requested 10. GPIORMIS (Port ...
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GPIORIC (Port R Interrupt Clear Register) Bit Bit Symbol − [31:8] − [7:3] [2] PR2IC − [1:0] [Description] a. <PR2IC> Interrupt clear register: Clears edge-sensitive interrupts. 0y0: Invalid 0y1: Clear request TENTATIVE Reset Type Value − Undefined Read as ...
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Port T Port T can be used as general-purpose input/output pins. Port T can also be used as USB external clock input (X1USB), UART function (U1CTSn, U1RXD, U1TXD), and SPI function (SP0DI, SP0DO, SP0CLK, SP0FSS) and pins. General-purpose input ...
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GPIOTDATA (Port T Data Register) Bit Bit Symbol − − [31:8] [7:0] PT7 to PT0 R/W [Description] a. <PT7 to PT0> Data register: Stores data. See notes on data registers for the bit mask function. 2. GPIOTDIR (Port T ...
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GPIOTFR1 (Port T Function Register 1) Bit Bit Symbol − [31:8] [7:0] PT7F1 to PT0F1 [Description] a. <PT7F1 to PT0F1> Function register 1: Controls the function setting. TENTATIVE Reset Type Value − Undefined Read as undefined. Written as zero. ...
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PORTU Port U can be used as general-purpose input/output pins pins. Port U can also be used as NAND controller function (NDD7 to NDD0) and, LCDC (LD7 to LD0). General-purpose input setting Function Data Value GPIOUDATA General-purpose input * ...
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GPIOUDATA (Port U Data Register) Bit Bit Symbol − − [31:8] [7:0] PU[7:0] R/W [Description] a. <PU[7:0]> Data register: Stores data. See notes on data registers for the bit mask function. 2. GPIOUDIR (Port U Data Direction Register) Bit ...
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GPIOUFR2 (Port U Function Register2) Bit Bit Symbol − [31:8] [7:0] PU7F2 to PU0F2 [Description] a. <PU7F2 to PU0F2> Function register 2: Controls the function setting. TENTATIVE Reset Type Value − Undefined Read as undefined. Write as zero. R/W ...
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PORTV Port V can be used as general-purpose input/output pins pins. Port V can also be used as NAND controller function (NDRBn, NDCE1n, NDCE0n, NDCLE, NDALE, NDWEn and NDREn) and LCDC function (LD15 to LD8). General-purpose input setting Function ...
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GPIOVDATA (Port V Data Register) Bit Bit Symbol − − [31:8] [7:0] PV[7:0] R/W [Description] a. <PV[7:0]> Data register: Stores data. See notes on data registers for the bit mask function. 2. GPIOVDIR (Port V Data Direction Register) Bit ...
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GPIOVFR2 (Port V Function Register2) Bit Bit Symbol − [31:8] [7:0] PV7F2 to PV0F2 [Description] a. <PV7F2 to PV0F2> Function register 2: Controls the function setting. TENTATIVE Reset Type Value − Undefined Read as undefined. Write as zero. R/W ...
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Notes • Procedure for using the interrupt function Interrupts can be detected in various modes depending on the sensitivity setting. The following procedure should be observed when the interrupt function is enabled (GPIOxIE = 1) or the interrupt mode ...
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MPMC This LSI contains two types of memory controller with different specifications. Depending on the connected external memory, one of two types of controllers (MPMC0/MPMC1) can be selected by setting the external pin SELMEMC (port SN0). By setting the ...