IDT79EB351 IDT, Integrated Device Technology Inc, IDT79EB351 Datasheet

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Evaluation Board Manual Evaluation Board Manual Evaluation Board Manual Evaluation Board Manual 6024 Silver Creek Valley Road, San Jose, California 95138 Telephone: (800) 345-7015 • (408) 284-8200 • FAX: (408) 284-2775 ©2005 Integrated Device Technology, Inc. ...

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Integrated Device Technology, Inc. reserves the right to make changes to its products or specifications at any time, without notice, in order to improve design or performance and to supply the best possible product. IDT does not assume any responsibility ...

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... Description of IDT79EB351 Notes Evaluation Board Introduction ..................................................................................................................................1-1 Revision History...........................................................................................................................1-1 Overview of Features...................................................................................................................1-1 Explanation of Features...............................................................................................................1-1 Block Diagram .............................................................................................................................1-2 Specification Summary ................................................................................................................1-2 2 Installation of 79EB351 Evaluation Board 79EB351 Installation....................................................................................................................2-1 Getting Started Quickly................................................................................................................2-1 Jumper and Switch Settings ........................................................................................................2-2 System Software - IDT/SIM .........................................................................................................2-5 Serial Port for CRT Video Terminal and Auxiliary Port ...

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Table of Contents 4 Schematics Notes 5 EPLD Equation 79EB351 Evaluation Board Manual Schematics Errata .......................................................................................................................4-1 Revision History .................................................................................................................4-1 Item #1 ...............................................................................................................................4-1 Item #2 ...............................................................................................................................4-2 Item #3 ...............................................................................................................................4-3 Schematics ..................................................................................................................................4-3 ii June 9, 2003 ...

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Figure 1.1 Notes Figure 4.1 Figure 4.2 Figure 4.3 79EB351 Evaluation Board Manual 79EB351 Evaluation Board Block Diagram ......................................................................1-2 79EB351 Bluewire List......................................................................................................4-1 79EB351 Top Layer..........................................................................................................4-2 79EB351 Bottom Layer.....................................................................................................4-3 iii List of Figures June 9, 2003 ...

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List of Figures Notes 79EB351 Evaluation Board Manual iv June 9, 2003 ...

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Table 2.1 Notes Table 2.2 Table 2.3 Table 2.4 Table 2.5 Table 2.6 Table 2.7 Table 2.8 Table 2.9 Table 2.10 Table 2.11 Table 2.12 Table 2.13 Table 2.14 Table 2.15 Table 3.1 Table 3.2 79EB351 Evaluation Board Manual J21 ...

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List of Tables Notes 79EB351 Evaluation Board Manual vi June 9, 2003 ...

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... DMA channels, reset circuitry, interrupts, timers, and UARTs. The RC32351 integrated processor is a complete CPU subsystem for embedded designs. The IDT79EB351 Evaluation Board provides an RC32351 evaluation tool.This board is highly config- urable and contains hardware options for various memory configurations. ...

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... Description of IDT79EB351 Evaluation Board Block Diagram Notes ( Specification Summary SDRAM EPROM FLASH SRAM Ethernet 79EB351 Evaluation Board Manual LOGIC Analyzer Connectors ETHERNET (MICTOR) PHY MII UARTS USB (E)JTAG SDRAM SRAM 32MB 256KB SODIMM (64Kx32) 1MB (256kx32) Figure 1.1 79EB351 Evaluation Board Block Diagram ...

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Installation Notes The primary installation steps are as follows: 1. Connecting a power source – This involves connecting an external power supply to the board. 2. Connecting a Video display terminal – This involves connecting an RS232C serial cable ...

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Installation of 79EB351 Evaluation Board Notes The CRT video terminal can be a VT100 type/ANSI terminal or emulator running with 9600 baud, 8 data bits, no parity, and 1 stop bit. RS232C connector, on the eval. Board uses a male ...

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Installation of 79EB351 Evaluation Board S1: DIP Switch 1 Notes SPDT switch. 0 means – position on the switch, 1 means + position. S3 and S4: Boot vector selection Selection of 79EB351 Mode Bits during Power-on/ Cold ...

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Installation of 79EB351 Evaluation Board Notes S4-3: S4-4: S4-5: Clock Multiplier To generate Pipeline clock, input clock is multiplied by clock multiplier. S4-6: S4-7: S4-8: In the case of booting from flash or booting from flash and programming flash: (CS0 ...

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Installation of 79EB351 Evaluation Board Notes Jumper selection: In case of booting from EPROM and programming flash: Switch configuration: Boot code vector bits [15:14] were hard wired in new EPLD code and switch (S3) 1&2 were used to select flash ...

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Installation of 79EB351 Evaluation Board Notes Initialization and System Start-up System start up is performed by turning on the power supply. If the power is already on, pressing the reset button will reinitialize the board. The board default configuration is ...

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Installation of 79EB351 Evaluation Board Notes J6: JTAG Connector All even Pins are GND. J5: EJTAG Connector for 79RC32351 79EB351 Evaluation Board Manual Pin Signal Color 7 COM BLACK 8 PWR_OK GRAY 9 +5VSB PURPLE 10 +12VDC YELLOW Table 2.8 ...

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Installation of 79EB351 Evaluation Board Logic Analyzer POD Connectors Notes Logic Analyzer POD Connector J7 Logic Analyzer POD Connector J8 79EB351 Evaluation Board Manual Logic Analyzer POD Connectors Pin Signal Pin 1 N GND 4 5 MIC1_CLK 6 ...

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Installation of 79EB351 Evaluation Board Notes Logic Analyzer POD Connector J9 79EB351 Evaluation Board Manual Logic Analyzer POD Connectors Pin Signal Pin 21 RST_N ...

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Installation of 79EB351 Evaluation Board Logic Analyzer POD Connector J11 Notes Logic Analyzer POD Connector J15 79EB351 Evaluation Board Manual Logic Analyzer POD Connectors Pin Signal Pin 1 N GND ATM_TXD7 8 9 ...

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Installation of 79EB351 Evaluation Board Notes 79EB351 Evaluation Board Manual Logic Analyzer POD Connectors Pin Signal Pin 25 D22 26 27 D21 28 29 D20 30 31 D19 32 33 D18 34 35 D17 36 37 D16 38 Table 2.15 ...

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Installation of 79EB351 Evaluation Board Notes 79EB351 Evaluation Board Manual Logic Analyzer POD Connectors June 9, 2003 ...

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... Introduction Notes This chapter provides information on the functional operation of the IDT79EB351 evaluation board for the RC32351 communications processor. For detailed schematics, refer to Chapter 4. For detailed PLD equations, refer to Chapter 5. Address Space Decoding Physical addresses for the resources on the 79EB351 board use the following typical memory map. ...

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Theory of Operation and Design Notes USB Device Speed Selection Notes Speed of a device is detected by pulling up the line. If the D+ line is pulled high (R34 installed), the device is at full speed. ...

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Schematics Errata Notes This section reflects the changes to the 79EB351 Evaluation Board (18-511-000). Revision History March 12, 2001: Rev 01, Item #1. January 18, 2002: Rev 02, added Item #2. June 9, 2003: Rev 03, added Item #3. Item ...

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Schematics Notes U35-16: Either cut and remove or lift this pin. Jumpers Lift U35 Pin 18 & jumper to U35 pin 17 Jumper from U35 pad 18 to U35 pin 21 Jumper from via adjacent to U35 pin 15 to ...

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Schematics Item #3 EPLD Code Did Not Support System Flash Programming or Control Wait/ack Input of CPU's Input by Multiple Devices The following revisions were made (Notation "Component location-Pin number" ex: J7-16): Added wire between J7-16 and U13-62 (else to ...

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SHEET DESCRIPTION 0 TABLE OF CONTENTS 1 CPU 2 SDRAM 3 EXPANSION CONNECTORS 4 BUFFERS SRAM, EPROM, TIMER 5 6 FLASH MEMORY ETHERNET PHY 7 ATM PHY 8 9 ATM MAGNETICS 10 EPLD, INTERRUPT STATUS UART 11 12 LCD, RESET, ...

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A ATM_TXD ATM_RXD D VDD_IO VDD_IO 79RC32T351-133 CPU_CLK 166 CLK SYSCLK COLDRST 72 COLDRST RST USB_CLK 77 USBD USBCLK USBD 3.3V/2.5V BR 104 BR OE WAITACK 167 WAITACK RW SYSCLK_SODIMM 145 SDCLKIN BG D0 124 D0 BWE0 D1 126 D1 ...

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D A +3.3V SDRAM_SODIMM 1 GND D0 3 DQ0 D1 5 DQ1 D2 7 DQ2 D3 9 DQ3 11 VDD D4 13 DQ4 D5 15 DQ5 D6 17 DQ6 D7 19 DQ7 21 GND BWE0_U 23 DQMB0 BWE1_U 25 DQMB1 ...

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CONN_64_SM_FEM SYS_CLK1 ATM_RXD0 13 14 ATM_TXD0 ATM_RXD1 15 16 ATM_TXD1 ATM_RXD2 17 18 ATM_TXD2 ATM_RXD3 19 20 ATM_TXD3 ATM_RXD4 21 22 ATM_TXD4 23 24 ...

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DB D ADDR BOE0 BDIR A 74ALVCH16244 1 1OE 48 2OE 25 3OE 24 4OE 3. 1A0 1Y0 46 3 1A1 1Y1 44 5 1A2 1Y2 A20 43 6 ADDR20 1A3 1Y3 A19 41 8 ADDR19 2A0 2Y0 ...

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DB ADDR 71V416S_15NS CS1 MSEL2 39 BLE MSEL3 40 BHE 3.3V ADDR2 1 A0 I/O0 ADDR3 2 A1 I/O1 ADDR4 3 A2 I/O2 ADDR5 4 A3 I/O3 5 ADDR6 A4 I/O4 ADDR7 ...

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DB FA RST BWE2 BWE0 FLASH_CS OE BWE3 BWE1 +3.3V 28F016S3_120NS RY/ VCC VCC VPP FA0 A0 DQ0 FA1 DQ1 FA2 ...

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LXT972 1 4 NC/OE VDD 22 OHMS 3. R30 1 GND OUT REFCLK/ RST 4 RESET LED/CFG1 39 PWRDWN LED/CFG2 33 PAUSE LED/CFG3 12 ADDR0 3 MDDIS MDIO MII_MDC 43 MDC MDINT 3.3V 34 ...

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LOAD 0 OHM RES FOR R79, R85, IN POSITION 77V1053 TXSOC 66 TXSOC 64 TXPRTY ATM_TXCLK 74 TXCLK ATM_TXEN 65 TXEN ATM_TXAD0 72 TXADR0 ATM_TXAD1 71 +3.3V TXADR1 70 TXADR2 68 TXADR3 67 TXADR4 77 RXCLK ATM_RXEN ...

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TX0+ 47 OHMS R1 TX0- 47 OHMS R3 RX0- 33 OHMS R66 1 470pF C80 2 R61 2.7K OHMS AVDD 16 R60 2.7K OHMS 13 470pF C79 14 RX0+ R65 33 OHMS TX1+ 47 OHMS R4 TX1- ...

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BOOT DB FA ADDR ATM_AD EPM7256AE-5 30 TCK/IO VCCIO 127 TMS/IO VCCIO 176 TDI/IO VCCIO PLD_CLK 184 GCLK1/I VCCIO RESET 182 GCLR/I VCCIO 183 OE1/I VCCIO 181 OE2/ VCCIO GCLK2/I VCCIO VCCIO VCCIO 3.3V 39 I/O TDO/IO INT_TIMER 115 I/O ...

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MAX3245 28 27 0.1UF C44 0.1UF C42 C1 0.1UF C40 C1- V- 0.1UF C36 1 26 C2+ VCC 2 25 C2- GND U0_TD 14 9 T1_IN T1_OUT U0_DTR 13 10 T2_IN T2_OUT U0_RTS 12 11 ...

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SN74CBTD3384 1 1OE 13 2OE DB0 1A1 1B1 DB1 4 5 1A2 1B2 DB2 7 6 1A3 1B3 DB3 8 9 1A4 1B4 DB4 11 10 1A5 1B5 DB5 14 15 2A1 2B1 DB6 17 16 ...

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BOOT BOOT15 BOOT14 BOOT13 BOOT12 BOOT11 BOOT10 BOOT9 BOOT8 BOOT7 BOOT6 BOOT4 BOOT3 BOOT2 BOOT1 BOOT0 SW_SPDT TGL/RKR A ...

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U0RI/TRST TDI TDO TMS TCK +5V QS3125 BOOT12 1 14 10E VCC BOOT8 4 20E 10 30E BOOT13 13 40E U0_RI U1_DSR U1_CTS U1_RD 12 11 U1RD_DMA2 4A ...

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A D CONN-2X19-FEM SYSCLK_SODIMM D31 7 8 D30 9 10 BWE3_U D29 11 12 BWE2_U D28 13 14 A20 D27 15 16 A19 D26 17 18 A18 D25 19 20 A17 D24 21 22 ...

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VDD_IO +3.3V MTG6 MTG7 Z1 MTG2 MTG1 MTG3 MTG8 MTG9 MTG4 MTG5 CHASSIS VDD_CORE +5V VDD_IO VDD_CORE VDD_2V5 +12V +5V AVDD FD20 FD19 FD4 TP6 FD1 FD17 FD25 FD2 FD5 FD30 TP5 FD21 FD7 FD29 FD14 ...

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SUBDESIGN EB351_reset Notes ( boot[15..0] :INPUT; db[15..8] :OUTPUT; d[7..0]:bidir; addr[20..0] : INPUT; a[22..21]:INPUT; fa[20..0] : OUTPUT; mem_sel_n[3..0] : OUTPUT; bwe_n[3..0] : INPUT; rw_n:input; reset_n : input; %183% coldrst_n: output; %123% lcd_e:output; lcd_rw_n:output; lcd_rs:output; atm_ad[7..0]:bidir; atm_clk:input; atm_ale:output; atm_rd:output; atm_wr:output; boe_n:input; cs4:input; ...

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EPLD Equation Notes % end bogus junk % VARIABLE BEGIN % 79EB351 Evaluation Board Manual cs3: input; %117% cs_combined: output; %118% rst : input; %34 input; %18% waitack_n : output; %8% busreq : output; %77% busgnt : input; ...

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EPLD Equation Notes % % Code changed for flash address % 79EB351 Evaluation Board Manual fa[20..0]=addr[20..0]; when 1 => fa[20..0]=(a21,addr[20..1]); when 2 => fa[20..0]= (gnd,a21,addr[20..2]); endcase; IF !cs2 THEN case boot[15..14] is when 0 => fa[20..0]=addr[20..0]; when 1 => fa[20..0]=(a21,addr[20..1]); ...

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EPLD Equation Notes END; 79EB351 Evaluation Board Manual atm_wr1_en.d = !bwe_n0 & !cs4 & !rw_n; atm_wr2_en.clk = !sys_clk; atm_wr2_en.clrn = dummyrst; atm_wr2_en.d = atm_wr1_en.q; atm_wr_en = atm_wr2_en.q; atm_ad[7] = tri(reset_n & (d[7] & atm_wr_en # addr[9] & atm_ale1), reset_n & ...