COP8-REF-FL1 National Semiconductor, COP8-REF-FL1 Datasheet - Page 43

• Manufacturer Part Number: COP8-REF-FL1
• Description: KIT REF DESIGN FOR COP8SDR9
• Manufacturer: National Semiconductor
• Series: COP8™r
• Type: MCUr

Specifications of COP8-REF-FL1

• Design Resources: COP8 Flash Ref Design Flyer
• Contents: PCB, Control Interface, Documentation and 9V Battery
• For Use With/related Products: COP8SDR9
• Lead Free Status / RoHS Status: Not applicable / Not applicable

9.0 Interrupts
SERVICE:
9.5 PORT L INTERRUPTS
Port L provides the user with an additional eight fully select-
able, edge sensitive interrupts which are all vectored into the
same service subroutine.
The interrupt from Port L shares logic with the wake-up
circuitry. The register WKEN allows interrupts from Port L to
be individually enabled or disabled. The register WKEDG
specifies the trigger condition to be either a positive or a
negative edge. Finally, the register WKPND latches in the
pending trigger conditions.
The GIE (Global Interrupt Enable) bit enables the interrupt
function.
A control flag, LPEN, functions as a global interrupt enable
for Port L interrupts. Setting the LPEN flag will enable inter-
rupts and vice versa. A separate global pending flag is not
needed since the register WKPND is adequate.
Since Port L is also used for waking the device out of the
HALT or IDLE modes, the user can elect to exit the HALT or
IDLE modes either with or without the interrupt enabled. If he
elects to disable the interrupt, then the device will restart
execution from the instruction immediately following the in-
struction that placed the microcontroller in the HALT or IDLE
modes. In the other case, the device will first execute the
interrupt service routine and then revert to normal operation.
(See HALT MODE for clock option wake-up information.)
9.6 INTERRUPT SUMMARY
The device uses the following types of interrupts, listed
below in order of priority:
1. The Software Trap non-maskable interrupt, triggered by
2. Maskable interrupts, triggered by an on-chip peripheral
3. While executing from the Boot ROM for ISP or virtual E2
the INTR (00 opcode) instruction. The Software Trap is
acknowledged immediately. This interrupt service rou-
tine can be interrupted only by another Software Trap.
The Software Trap should end with two RPND instruc-
tions followed by a re-start procedure.
block or an external device connected to the device.
Under ordinary conditions, a maskable interrupt will not
interrupt any other interrupt routine in progress. A
maskable interrupt routine in progress can be inter-
rupted by the non-maskable interrupt request. A
maskable interrupt routine should end with an RETI
instruction or, prior to restoring context, should return to
execute the VIS instruction. This is particularly useful
when exiting long interrupt service routines if the time
between interrupts is short. In this case the RETI instruc-
tion would only be executed when the default VIS rou-
tine is reached.
operations, the hardware will disable interrupts from oc-
curring. The hardware will leave the GIE bit in its current
state, and if set, the hardware interrupts will occur when
execution is returned to Flash Memory. Subsequent in-
terrupts, during ISP operation, from the same interrupt
source will be lost.
.
RBIT,EXPND,PSW
.
.
.
RET I
(Continued)
; Interrupt Service Routine
; Reset ext interrupt pend. bit
; Return, set the GIE bit
43
10.0 WATCHDOG/CLOCK
MONITOR
The device contains a user selectable WATCHDOG and
clock monitor. The following section is applicable only if the
WATCHDOG feature has been selected in the Option regis-
ter. The WATCHDOG is designed to detect the user program
getting stuck in infinite loops resulting in loss of program
control or “runaway” programs.
The WATCHDOG logic contains two separate service win-
dows. While the user programmable upper window selects
the WATCHDOG service time, the lower window provides
protection against an infinite program loop that contains the
WATCHDOG service instruction. The WATCHDOG uses the
Idle Timer (T0) and thus all times are measured in Idle Timer
Clocks.
The Clock Monitor is used to detect the absence of a clock or
a very slow clock below a specified rate on t
The WATCHDOG consists of two independent logic blocks:
WD UPPER and WD LOWER. WD UPPER establishes the
upper limit on the service window and WD LOWER defines
the lower limit of the service window.
Servicing the WATCHDOG consists of writing a specific
value to a WATCHDOG Service Register named WDSVR
which is memory mapped in the RAM. This value is com-
posed of three fields, consisting of a 2-bit Window Select, a
5-bit Key Data field, and the 1-bit Clock Monitor Select field.
Table 25 shows the WDSVR register.
The lower limit of the service window is fixed at 2048 Idle
Timer Clocks. Bits 7 and 6 of the WDSVR register allow the
user to pick an upper limit of the service window.
Table 26 shows the four possible combinations of lower and
upper limits for the WATCHDOG service window. This flex-
ibility in choosing the WATCHDOG service window prevents
any undue burden on the user software.
Bits 5, 4, 3, 2 and 1 of the WDSVR register represent the
5-bit Key Data field. The key data is fixed at 01100. Bit 0 of
the WDSVR Register is the Clock Monitor Select bit.
Window
TABLE 25. WATCHDOG Service Register (WDSVR)
X
7
Select
Interrupts may occur, however, between setting the ISP
KEY and executing the JSRB instruction. It is recom-
menden that the user globally disable interrupts before
setting the key and reenable interrupts immediately
upon returning from the Boot ROM.
X
6
0
5
1
4
Key Data
1
3
0
2
0
1
C
.
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Monitor
Clock
Y
0