HW-V5-PCIE2-UNI-G Xilinx Inc, HW-V5-PCIE2-UNI-G Datasheet
HW-V5-PCIE2-UNI-G
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HW-V5-PCIE2-UNI-G Summary of contents
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R DS100 (v5.0) February 6, 2009 General Description The Virtex®-5 family provides the newest most powerful features in the FPGA market. Using the second generation ASMBL™ (Advanced Silicon Modular Block) column-based architecture, the Virtex-5 family contains five distinct platforms (sub-families), ...
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Virtex-5 Family Overview Table 1: Virtex-5 FPGA Family Members Configurable Logic Blocks (CLBs) Device Max Array Virtex-5 Distributed (1) (Row x Col) Slices RAM (Kb) XC5VLX30 4,800 320 XC5VLX50 120 x 30 7,200 480 XC5VLX85 120 x ...
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R Virtex-5 FPGA Logic • On average, one to two speed grade improvement over Virtex-4 devices • Cascadable 32-bit variable shift registers or 64-bit distributed memory capability • Superior routing architecture with enhanced diagonal routing supports block-to-block connectivity with minimal ...
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Virtex-5 Family Overview Digitally Controlled Impedance (DCI) Active I/O Termination • Optional series or parallel termination • Temperature and voltage compensation • Makes board layout much easier − Reduces resistors − Places termination in the ideal location, at the signal ...
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R RocketIO GTP Transceivers (LXT/SXT only) • Full-duplex serial transceiver capable of 100 Mb/s to 3.75 Gb/s baud rates • 8B/10B, user-defined FPGA logic encoding options • Channel bonding support • CRC generation and checking • Programmable pre-emphasis ...
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Virtex-5 Family Overview Architectural Description Virtex-5 FPGA Array Overview Virtex-5 devices are user-programmable gate arrays with various configurable elements and embedded cores optimized for high-density and high-performance system designs. Virtex-5 devices implement the following functionality: • I/O blocks provide the ...
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R Virtex-5 FPGA Features This section briefly describes the features of the Virtex-5 family of FPGAs. Input/Output Blocks (SelectIO) IOBs are programmable and can be categorized as follows: • Programmable single-ended or differential (LVDS) operation • Input block with an ...
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Virtex-5 Family Overview Global Clocking The CMTs and global-clock multiplexer buffers provide a complete solution for designing high-speed clock networks. Each CMT contains two DCMs and one PLL. The DCMs and PLLs can be used independently or extensively cascaded. Up ...
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R Virtex-5 LXT, SXT, TXT, and FXT Platform Features This section briefly describes blocks available only in LXT, SXT, TXT, and FXT devices. Tri-Mode (10/100/1000 Mb/s) Ethernet MACs Virtex-5 LXT, SXT, TXT, and FXT devices contain up to eight embedded ...
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Virtex-5 Family Overview Virtex-5 TXT and FXT Platform Features This section describes blocks only available in TXT and FXT devices. RocketIO GTX Serial Transceivers (TXT/FXT channels RocketIO serial transceivers capable of running 150 Mb/s to 6.5 Gb/s ...
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R Application Notes and Reference Designs Application notes and reference designs written specifically for the Virtex-5 family are available on the Xilinx website at: http://www.xilinx.com/virtex5 Virtex-5 Device and Package Combinations and Maximum I/Os Table 2: Virtex-5 Device and Package Combinations ...
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Virtex-5 Family Overview Virtex-5 FPGA Ordering Information Virtex-5 FPGA ordering information shown in X-Ref Target - Figure 1 Example: XC5VLX50T-1FFG665C Device Type Speed Grade (-1, -2, -3 (1) ) Note speed grade is not available in all devices ...
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R Notice of Disclaimer THE XILINX HARDWARE FPGA AND CPLD DEVICES REFERRED TO HEREIN (“PRODUCTS”) ARE SUBJECT TO THE TERMS AND CONDITIONS OF THE XILINX LIMITED WARRANTY WHICH CAN BE VIEWED AT http://www.xilinx.com/warranty.htm. THIS LIMITED WARRANTY DOES NOT EXTEND TO ...