AD9446-100LVDS/PCB Analog Devices Inc, AD9446-100LVDS/PCB Datasheet - Page 8

• Manufacturer Part Number: AD9446-100LVDS/PCB
• Description: BOARD EVAL FOR AD9446-100 LVDS
• Manufacturer: Analog Devices Inc

Specifications of AD9446-100LVDS/PCB

• Number Of Adc's: 1
• Number Of Bits: 16
• Sampling Rate (per Second): 100M
• Data Interface: Parallel
• Inputs Per Adc: 1 Single Ended
• Input Range: 2 ~ 4 Vpp
• Power (typ) @ Conditions: 2.6W @ 100MSPS
• Voltage Supply Source: Single
• Operating Temperature: -40°C ~ 85°C
• Utilized Ic / Part: AD9446
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

AD9446
ABSOLUTE MAXIMUM RATINGS
Table 5.
Parameter
ELECTRICAL
ENVIRONMENTAL
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
AVDD1
AVDD2
DRVDD
AGND
AVDD1
AVDD2
AVDD2
D0± to D15±
CLK+/CLK−
OUTPUT MODE,
VIN+, VIN−
VREF
SENSE
REFT, REFB
Storage Temperature
Operating Temperature
Lead Temperature
Junction Temperature
DCS MODE, DFS
Range
Range
(Soldering 10 sec)
With
Respect
to
AGND
AGND
DGND
DGND
DRVDD
DRVDD
AVDD1
DGND
AGND
AGND
AGND
AGND
AGND
AGND
Rating
−0.3 V to +4 V
−0.3 V to +6 V
−0.3 V to +4 V
−0.3 V to +0.3 V
−4 V to +4 V
−4 V to +6 V
−4 V to +6 V
–0.3 V to DRVDD + 0.3 V
–0.3 V to AVDD1 + 0.3 V
–0.3 V to AVDD1 + 0.3 V
–0.3 V to AVDD2 + 0.3 V
–0.3 V to AVDD1 + 0.3 V
–0.3 V to AVDD1 + 0.3 V
–0.3 V to AVDD1 + 0.3 V
–65°C to +125°C
–40°C to +85°C
300°C
150°C
Rev. 0 | Page 8 of 36
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
THERMAL RESISTANCE
The heat sink of the AD9446 package must be soldered to
ground.
Table 6.
Package Type
100-lead TQFP/EP
Typical θ
board in still air.
Typical θ
in still air.
Typical θ
the thermal resistance through heat sink path.
Airflow increases heat dissipation, effectively reducing θ
more metal directly in contact with the package leads from
metal traces through holes, ground, and power planes reduces
the θ
the ground plane.
JA
. It is required that the exposed heat sink be soldered to
JA
JB
JC
= 8.3°C/W (heat sink soldered) for multilayer board
= 19.8°C/W (heat sink soldered) for multilayer
= 2°C/W (junction to exposed heat sink) represents
θ
19.8
JA
θ
8.3
JB
θ
2
JC
Unit
°C/W
JA
. Also,