HW-SPAR3-SK-UNI-G Xilinx Inc, HW-SPAR3-SK-UNI-G Datasheet

KIT STARTER SPARTAN-3

HW-SPAR3-SK-UNI-G

Manufacturer Part Number
HW-SPAR3-SK-UNI-G
Description
KIT STARTER SPARTAN-3
Manufacturer
Xilinx Inc
Series
Spartan-3r
Type
FPGA Configurationr
Datasheet

Specifications of HW-SPAR3-SK-UNI-G

Contents
Board, Cable, Software, Datasheets and User Manual
For Use With/related Products
Spartan-3
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
122-1521

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Part Number:
HW-SPAR3-SK-UNI-G
Manufacturer:
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Spartan-3 FPGA
Starter Kit Board
User Guide
UG130 (v1.2) June 20, 2008
R

Related parts for HW-SPAR3-SK-UNI-G

HW-SPAR3-SK-UNI-G Summary of contents

Page 1

Spartan-3 FPGA Starter Kit Board User Guide UG130 (v1.2) June 20, 2008 R ...

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Xilinx is disclosing this Document and Intellectual Property (hereinafter “the Design”) to you for use in the development of designs to operate on, or interface with Xilinx FPGAs. Except as stated herein, none of the Design may be copied, reproduced, ...

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Table of Contents Preface: About This Guide Guide Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

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R Chapter 10: Platform Flash Configuration Storage Platform Flash Jumper Options (JP1) “Default” Option “Flash Read” Option “Disable” Option Chapter 11: JTAG Programming/Debugging Ports JTAG Header (J7) Parallel Cable IV/MultiPro Desktop Tool JTAG Header (J5) Chapter 12: Power Distribution AC ...

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R About This Guide This user guide describes the components and operation of the Spartan Kit Board. Guide Contents This manual contains the following chapters: • Chapter 1, “Introduction” • Chapter 2, “Fast, Asynchronous SRAM” • Chapter 3, “Four-Digit, Seven-Segment ...

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R 6 www.xilinx.com Spartan-3 FPGA Starter Kit Board User Guide Preface: About This Guide UG130 (v1.2) June 20, 2008 ...

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R Introduction The Xilinx Spartan evaluation platform for Spartan-3 FPGA designs. Key Components and Features Figure 1-1 components and features: • 200,000-gate Xilinx package (XC3S200FT256) ♦ 4,320 logic cell equivalents ♦ Twelve 18K-bit block RAMs (216K bits) ♦ Twelve 18x18 ...

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R 2 XCF02S 2Mbit Configuration PROM 3 Platform Flash Option Jumpers 256Kx16 10ns SRAM 4 256Kx16 10ns SRAM 8-color 5 VGA Port 6 RS-232 Port Serial Port 9 PS/2 Port 4 Character 10 7-Segment LED 11 8 Slide Switches Power ...

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Component Locations • 50 MHz crystal oscillator clock source (bottom side of board, see • Socket for an auxiliary crystal oscillator clock source • FPGA configuration mode selected via jumper settings • Push button switch to force FPGA reconfiguration (FPGA ...

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Expansion Connector DONE PROG 25 POWER POWER Figure 1-2: Xilinx Spartan-3 Starter Kit Board (Top Side MHz Figure 1-3: Xilinx Spartan-3 Starter Kit Board (Bottom Side ...

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R Fast, Asynchronous SRAM The Spartan surface-mounted to the backside of the board. The memory array includes two 256Kx16 ISSI IS61LV25616AL-10T schematic appears in Spartan-3 FPGA Starter Kit Board User Guide UG130 (v1.2) June 20, 2008 ® -3 FPGA Starter ...

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R The SRAM array forms either a single 256Kx32 SRAM memory or two independent 256Kx16 arrays. Both SRAM devices share common write-enable (WE#), output-enable (OE#), and address (A[17:0]) signals. However, each device has a separate chip select enable (CE#) control ...

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Write Enable and Output Enable Control Signals Write Enable and Output Enable Control Signals Both 256Kx16 SRAMs share common output enable (OE#) and write enable (WE#) control lines, as shown in Connector (refer to Table 2-2: External SRAM Control Signal ...

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R Table 2-4: SRAM IC11 Connections CE2 (chip enable IC11) UB2 (upper byte enable IC11) LB2 (lower byte enable IC11) 14 Signal FPGA Pin IO15 N1 IO14 M1 IO13 K2 IO12 C3 IO11 F5 IO10 G1 IO9 E2 IO8 D2 ...

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R Four-Digit, Seven-Segment LED Display The Spartan controlled by FPGA user-I/O pins, as shown in control signals to light individual LED segments. Each individual character has a separate anode control input. A detailed schematic for the display appears in The ...

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R Table 3-1: FPGA Connections to Seven-Segment Display (Active Low) Table 3-2: Digit Enable (Anode Control) Signals (Active Low) Anode Control FPGA Pin Table 3-3: Display Characters and Resulting LED Segment Control Values Character ...

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The LED control signals are time-multiplexed to display data on all four characters, as shown in Figure select the specified character by driving the associated anode control signal Low. Through persistence of vision, the human brain perceives that all four ...

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R 18 Chapter 3: Four-Digit, Seven-Segment LED Display www.xilinx.com Spartan-3 FPGA Starter Kit Board User Guide UG130 (v1.2) June 20, 2008 ...

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R Switches and LEDs Slide Switches The Spartan Figure 1-2. The switches are located along the lower edge of the board, toward the right edge. The switches are labeled SW7 through SW0. Switch SW7 is the left-most switch, and SW0 ...

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R LEDs The Spartan-3 Starter Kit board has eight individual surface-mount LEDs located above the push button switches, indicated by through LED0. LED7 is the left-most LED, LED0 the right-most LED. FPGA connections to the LEDs. Table 4-3: LED Connections ...

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R VGA Port The Spartan indicated as LCD displays using a standard monitor cable. DB15 Connector Red Green Blue 3 8 Horizontal Sync Vertical Sync GND Figure ...

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R Table 5-1: VGA Port Connections to the Spartan-3 FPGA Red (R) Green (G) Blue (B) Horizontal Sync (HS) Vertical Sync (VS) Each color line has a series resistor to provide 3-bit color, with one bit each for Red, Green, ...

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Signal Timing for a 60Hz, 640x480 VGA Display same signal timings as CRT displays. Consequently, the following discussion pertains to both CRTs and LCD displays. Within a CRT display, current waveforms pass through the coils to produce magnetic fields that ...

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R Modern VGA displays support multiple display resolutions, and the VGA controller dictates the resolution by producing timing signals to control the raster patterns. The controller produces TTL-level synchronizing pulses that set the frequency at which current flows through the ...

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VGA Signal Timing Generally, a counter clocked by the pixel clock controls the horizontal timing. Decoded counter values generate the HS signal. This counter tracks the current pixel display location on a given row. A separate counter tracks the vertical ...

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R 26 www.xilinx.com Spartan-3 FPGA Starter Kit Board User Guide Chapter 5: VGA Port UG130 (v1.2) June 20, 2008 ...

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R PS/2 Mouse/Keyboard Port The Spartan standard 6-pin mini-DIN connector, labeled J3 on the board and indicated as Figure 1-2. connector. Only pins 1 and 5 of the connector attach to the FPGA. A detailed schematic appears in Table 6-1: ...

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R bidirectional keyboard communications. As shown in mouse writes a bit on the data line when the clock signal is High, and the host reads the data line when the clock signal is Low. Table 6-2: PS/2 Bus Timing Symbol ...

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Keyboard ESC TAB Caps Lock ...

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R The following site contains more information on PS/2 keyboard interfaces: • The PS/2 Keyboard Interface http://www.computer-engineering.org/index.php?title=PS/2_Keyboard_Interface Mouse A mouse generates a clock and data signal when moved; otherwise, these signals remain High indicating the Idle state. Each time the ...

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Voltage Supply an overflow occurs. If the mouse moves continuously, the 33-bit transmissions repeat every so. The L and R fields in the status byte indicate Left and Right button presses. A ‘1’ indicates that the associated ...

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R 32 Chapter 6: PS/2 Mouse/Keyboard Port www.xilinx.com Spartan-3 FPGA Starter Kit Board User Guide UG130 (v1.2) June 20, 2008 ...

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R RS-232 Serial Port The Spartan receive signals appear on the female DB9 connector, labeled J2, indicated as Figure 1-2. The connector is a DCE-style port and connects to the DB9 DTE-style serial port connector available on most personal computers ...

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R turn, converts the logic value to the appropriate RS-232 voltage level. Likewise, the Maxim device converts the RS-232 serial input data to LVTTL levels for the FPGA. A series resistor between the Maxim output pin and the FPGA’s RXD ...

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R Clock Sources The Spartan clock oscillator source and an optional socket for another clock oscillator source. Figure A-5 The 50 MHz clock oscillator is mounted on the bottom side of the board, indicated as in Figure A-5. Use the ...

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R FPGA Configuration Modes and Functions FPGA Configuration Mode Settings In most applications for the Spartan boots from the on-board Platform Flash memory whenever power is applied or the PROG push button is pressed. However, the board supports all the ...

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Program Push Button/DONE Indicator LED Table 9-1: Header J8 Controls the FPGA Configuration Mode (Continued) Configuration Header J8 Jumper JP1 Mode Settings <M0:M1:M2> Slave Parallel J8 GND <0:1:1> JTAG J8 GND <1:0:1> Program Push ...

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R Platform Flash Configuration Storage The Spartan store FPGA configuration data and potentially additional non-volatile data, including MicroBlaze application code. To configure the FPGA from Platform Flash memory, all three jumpers must be installed on the J8 header, indicated as ...

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Read” Option “Flash Read” Option The Spartan-3 Starter Kit Board includes a 2Mbit Platform Flash configuration PROM. The XC3S200 FPGA on the board only requires slightly less than 1Mbit for configuration data. The remainder of the Platform Flash is ...

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R Additional FPGA logic is required to read the Platform Flash data, as described in the following application note. • XAPP694: Reading User Data from Configuration PROMs www.xilinx.com/support/documentation/application_notes/xapp694.pdf “Disable” Option If the JP1 jumper is removed, then the Platform Flash ...

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R JTAG Programming/Debugging Ports The Spartan chain. Both the Spartan-3 FPGA and the Platform Flash devices are part of the JTAG chain, as shown in signals from various supported JTAG download and debugging cables. A Digilent JTAG3 low-cost parallel to ...

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... Parallel Cable IV (PC IV) http://www.xilinx.com/products/devkits/HW-PC4.htm Use the 14-pin ribbon cable supplied with both cables to connect to the J5 header. DO NOT use the flying leads that are also provided with some cables. Although the MultiPro Desktop Tool and the Parallel Cable IV support multiple FPGA configuration modes, the Spartan-3 Starter Kit board only supports the JTAG configuration method ...

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Parallel Cable IV/MultiPro Desktop Tool JTAG Header (J5) Figure 11-3: Use 14-Pin Ribbon Cable to Connect Parallel Cable IV or the MultiPro Spartan-3 FPGA Starter Kit Board User Guide UG130 (v1.2) June 20, 2008 Red trace indicates pin 1 21 ...

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R 44 Chapter 11: JTAG Programming/Debugging Ports www.xilinx.com Spartan-3 FPGA Starter Kit Board User Guide UG130 (v1.2) June 20, 2008 ...

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R Power Distribution AC Wall Adapter The Spartan produces a +5V DC output. Connect the AC wall adapter to the barrel connector along the left edge of the board, indicated as To disconnect power, remove the AC adapter from the ...

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R Overall, the 5V DC switching power adapter that connects to AC wall power powers the board. A 3.3V regulator, powered by the 5V DC supply, provides power to the inputs of the 2.5V and 1.2V regulators. Similarly, the 3.3V ...

Page 47

R Expansion Connectors and Boards Expansion Connectors The Spartan A2, and B1. The A1 and A2 connectors, indicated as are on the top edge of the board. Connector the top left, and the top ...

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R Table 13-1: Expansion Connector Features Connector User I Data[7:0] to IC10 only Each port offers some ability to program the FPGA on the Spartan-3 Starter Kit Board. For example, port A1 provides additional ...

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Expansion Connectors A1 Connector Pinout The A1 expansion connector is located along the top edge of the board, on the left, as indicated by FPGA connections are specified in parentheses. Table 13-2: Pinout for A1 Expansion Connector Schematic Name FPGA ...

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R The A1 expansion connector shares connections with the 256Kx16 SRAM devices, specifically the SRAM address lines, the OE# and WE# control signals, and the eight least- significant data lines to SRAM IC10 only. Similarly, the JTAG chain is available ...

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Expansion Connectors B1 Connector Pinout The B1 expansion connector is located on the right edge of the board, as indicated by Figure 1-2. specified in parentheses. Most of the B1 expansion connector pins connect only with the FPGA and are ...

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R Expansion Boards Various expansion boards plug into the A1, A2 connectors as listed below: • Spartan-3 Starter Kit Expansion Boards www.xilinx.com/products/boards/DO-SPAR3-DK/boards/daughtercards.htm • Digilent Expansion Boards www.digilentinc.com/Products/Catalog.cfm?Nav1=Products&Nav2=Peripheral&Cat=Peripheral • Digilent Breakout Probe Header (TPH1) http://www.digilentinc.com/Products/Catalog.cfm?Cat=Accessory • Digilent Breadboard (DBB1) ...

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R Board Schematics This appendix provides the schematics for the Spartan • Figure • Figure Display” • Figure • Figure Jumper JP1” • Figure • Figure • Figure Interface” • Figure • Figure Spartan-3 FPGA Starter Kit Board User Guide ...

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R Figure A-1: A1, A2, and B1 Expansion Connectors 54 Appendix A: Board Schematics www.xilinx.com Spartan-3 FPGA Starter Kit Board User Guide UG130_ApA_01_051305 UG130 (v1.2) June 20, 2008 ...

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Figure A-2: Slide Switches, Push Buttons, LEDs, and Four-Character 7-Segment Display Spartan-3 FPGA Starter Kit Board User Guide UG130 (v1.2) June 20, 2008 www.xilinx.com R UG130_ApA_02_051305 55 ...

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R Figure A-3: Voltage Regulators, JP2 Jumper Setting for PS/2 Port Voltage 56 Appendix A: Board Schematics www.xilinx.com Spartan-3 FPGA Starter Kit Board User Guide UG130_ApA_03_042704 UG130 (v1.2) June 20, 2008 ...

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Figure A-4: FPGA Configuration Interface, Platform Flash, JTAG Connections, Jumper JP1 Spartan-3 FPGA Starter Kit Board User Guide UG130 (v1.2) June 20, 2008 www.xilinx.com R UG130_ApA_04_051305 57 ...

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R Figure A-5: FPGA I/O Connections, Clock Sources 58 Appendix A: Board Schematics www.xilinx.com Spartan-3 FPGA Starter Kit Board User Guide UG130_ApA_05_051305 UG130 (v1.2) June 20, 2008 ...

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Figure A-6: Power Decoupling Capacitors Spartan-3 FPGA Starter Kit Board User Guide UG130 (v1.2) June 20, 2008 www.xilinx.com R UG130_ApA_06_051305 59 ...

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R Figure A-7: RS-232 Serial Port, VGA Port, PS/2 Port, Parallel Cable IV JTAG Interface 60 Appendix A: Board Schematics www.xilinx.com Spartan-3 FPGA Starter Kit Board User Guide UG130_ApA_07_051305 UG130 (v1.2) June 20, 2008 ...

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Figure A-8: Spartan-3 FPGA Starter Kit Board User Guide UG130 (v1.2) June 20, 2008 2x256Kx16 Fast Asynchronous SRAM Interface www.xilinx.com R UG130_ApA_08_051305 61 ...

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R Figure A-9: Digilent JTAG3 Low-Cost JTAG Download/Debug Cable 62 Appendix A: Board Schematics www.xilinx.com Spartan-3 FPGA Starter Kit Board User Guide UG130_ApA_09_042604 UG130 (v1.2) June 20, 2008 ...

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R Reference Material for Major Components Table B-1 lists the major components on the Spartan full part numbers and links to complete device data sheets. Table B-1: Major Components and Data Sheet Links Device Vendor Xilinx, Inc. 1 (IC1) Xilinx, ...

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R http://www.xilinx.com/products/boards/s3_sk_promo.htm PN 0402292 www.xilinx.com Spartan-3 FPGA Starter Kit Board User Guide UG130 (v1.2) June 20, 2008 ...

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