SW006012 Microchip Technology, SW006012 Datasheet - Page 110

• Manufacturer Part Number: SW006012
• Description: C COMPILER FOR DSPIC30F FAMILY
• Manufacturer: Microchip Technology
• Type: MPLAB® C30 Compilerr
• Series: PIC24 & DsPICr

Specifications of SW006012

• Supported Families: PIC24, DsPIC30F And DsPIC33F
• Core Architecture: PIC, DsPIC
• Kit Contents: Software And Docs
• Mcu Supported Families: PIC24 MCUs And DsPIC DSCs
• Tool Type: Compiler
• Processor Series: PIC24, dsPIC
• Lead Free Status / RoHS Status: Not applicable / Not applicable
• For Use With/related Products: dsPIC30F
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

MPLAB
7.5
7.6
7.7
DS51284F-page 104
INTERRUPT SERVICE ROUTINE CONTEXT SAVING
LATENCY
NESTING INTERRUPTS
®
C30 User’s Guide
Interrupts, by their very nature, can occur at unpredictable times. Therefore, the
interrupted code must be able to resume with the same machine state that was present
when the interrupt occurred.
To properly handle a return from interrupt, the setup (prologue) code for an ISR function
automatically saves the compiler-managed working and special function registers on
the stack for later restoration at the end of the ISR. You can use the optional save
parameter of the interrupt attribute to specify additional variables and special
function registers to be saved and restored.
In certain applications, it may be necessary to insert assembly statements into the
interrupt service routine immediately prior to the compiler-generated function prologue.
For example, it may be required that a semaphore be incremented immediately on
entry to an interrupt service routine. This can be done as follows:
void
__
There are two elements that affect the number of cycles between the time the interrupt
source occurs and the execution of the first instruction of your ISR code. These are:
• Processor Servicing of Interrupt – The amount of time it takes the processor to
• ISR Code – MPLAB C30 saves the registers that it uses in the ISR. This includes
The dsPIC30F devices support nested interrupts. Since processor resources are saved
on the stack in an ISR, nested ISR’s are coded in just the same way as non-nested
ones. Nested interrupts are enabled by clearing the NSTDIS (nested interrupt disable)
bit in the INTCON1 register. Note that this is the default condition as the dsPIC30F
device comes out of reset with nested interrupts enabled. Each interrupt source is
assigned a priority in the Interrupt Priority Control registers (IPCn). If there is a pending
Interrupt Request (IRQ) with a priority level equal to or greater than the current proces-
sor priority level in the Processor Status register (CPUPRI field in the ST register), an
interrupt will be presented to the processor.
recognize the interrupt and branch to the first address of the interrupt vector. To
determine this value refer to the processor data sheet for the specific processor
and interrupt source being used.
the working registers and the RCOUNT special function register. Moreover, if the
ISR calls an ordinary function, then the compiler will save all the working registers
and RCOUNT, even if they are not all used explicitly in the ISR itself. This must be
done, because the compiler cannot know, in general, which resources are used by
the called function.
isr0(void);
attribute
__
((
__
interrupt
__
(
__
preprologue
__
("inc _semaphore"))))
© 2007 Microchip Technology Inc.