SW006012 Microchip Technology, SW006012 Datasheet - Page 112

• Manufacturer Part Number: SW006012
• Description: C COMPILER FOR DSPIC30F FAMILY
• Manufacturer: Microchip Technology
• Type: MPLAB® C30 Compilerr
• Series: PIC24 & DsPICr

Specifications of SW006012

• Supported Families: PIC24, DsPIC30F And DsPIC33F
• Core Architecture: PIC, DsPIC
• Kit Contents: Software And Docs
• Mcu Supported Families: PIC24 MCUs And DsPIC DSCs
• Tool Type: Compiler
• Processor Series: PIC24, dsPIC
• Lead Free Status / RoHS Status: Not applicable / Not applicable
• For Use With/related Products: dsPIC30F
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

MPLAB
7.9
DS51284F-page 106
SHARING MEMORY BETWEEN INTERRUPT SERVICE ROUTINES AND
MAINLINE CODE
®
C30 User’s Guide
Care must be taken when modifying the same variable within a main or low-priority
Interrupt Service Routine (ISR) and a high-priority ISR. Higher priority interrupts, when
enabled, can interrupt a multiple instruction sequence and yield unexpected results
when a low-priority function has created a multiple instruction Read-Modify-Write
sequence accessing the same variable. Therefore, embedded systems must imple-
ment an atomic operation to ensure that the intervening high-priority ISR will not write
to the same variable from which the low-priority ISR has just read, but has not yet
completed its write.
An atomic operation is one that cannot be broken down into its constituent parts - it
cannot be interrupted. Depending upon the particular architecture involved, not all C
expressions translate into an atomic operation. On dsPIC DSC devices, these expres-
sions mainly fall into the following categories: 32-bit expressions, floating point arith-
metic, division, and operations on multi-bit bitfields. Other factors will determine
whether or not an atomic operation will be generated, such as memory model settings,
optimization level and resource availability.
Consider the general expression:
The operator (op) may or may not be atomic, based on device architecture. In any
event, the compiler may not be able to generate the atomic operation in all instances -
this will very much depend upon several factors:
• the availability of an appropriate atomic machine instruction
• the resource availability - special registers or other constraints
• the optimization level, and other options that affect data/code placement
Without knowledge of the architecture, it is reasonable to assume that the general
expression requires two reads, one for each operand and one write to store the result.
Several difficulties may arise in the presence of interrupt sequences; they very much
depend on the particular application.
7.9.1
Here are some examples:
EXAMPLE 7-1:
If it is required that bar and baz match, (i.e., are updated synchronously with each
other), there is a possible hazard if either bar or baz can be updated within a higher
priority interrupt expression. Here are some sample flow sequences:
1. Safe:
foo = bar op baz;
read bar
read baz
perform operation
write back result to foo
Development Issues
BAR MUST MATCH BAZ
© 2007 Microchip Technology Inc.