74lvth16646 Fairchild Semiconductor, 74lvth16646 Datasheet
74lvth16646
Related parts for 74lvth16646
74lvth16646 Summary of contents
Page 1
... Features Input and output interface capability to systems Bushold data inputs eliminate the need for external pull-up resistors to hold unused inputs (74LVTH16646) Also available without bushold feature (74LVT16646) Live insertion/extraction permitted Power Up/Down high impedance provides glitch-free bus loading Outputs source/sink 32 mA ...
Page 2
Connection Diagram Truth Table (Note 1) Inputs OE DIR CPAB CPBA SAB ...
Page 3
Functional Description In the transceiver mode, data present at the HIGH imped- ance port may be stored in either the register or both. The select (SAB , SBA ) controls can multiplex n n stored and real-time. ...
Page 4
Logic Diagrams Please note that these diagrams are provided only for the understanding of logic operations and should not be used to estimate propagation delays. www.fairchildsemi.com 4 ...
Page 5
Absolute Maximum Ratings Symbol Parameter V Supply Voltage Input Voltage Output Voltage Input Diode Current Output Diode Current Output Current Supply Current ...
Page 6
... Increase in Power Supply Current CC (Note 7) Note 4: Applies to bushold version only (74LVTH16646) Note 5: An external driver must source at least the specified current to switch from LOW-to-HIGH. Note 6: An external driver must sink at least the specified current to switch from HIGH-to-LOW. Note 7: This is the increase in supply current for each input that is at the specified voltage level rather than V ...
Page 7
AC Electrical Characteristics Symbol Parameter f Maximum Clock Frequency MAX t Propagation Delay PLH t CPAB or CPBA PHL t Propagation Delay PLH t Data PHL t Propagation Delay PLH t SBA ...
Page 8
Physical Dimensions inches (millimeters) unless otherwise noted 56-Lead Shrink Small Outline Package (SSOP), JEDEC MO-118, 0.300" Wide www.fairchildsemi.com Package Number MS56A 8 ...
Page 9
Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves ...