74VHC374M Fairchild Semiconductor, 74VHC374M Datasheet
74VHC374M
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74VHC374M Summary of contents
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... Number Number 74VHC374M M20B 74VHC374SJ M20D 74VHC374MTC MTC20 Surface mount packages are also available on Tape and Reel. Specify by appending the suffix letter “X” to the ordering number. Pb-Free package per JEDEC J-STD-020B. Connection Diagram ©1992 Fairchild Semiconductor Corporation 74VHC374 Rev. 1.3 ...
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... LOW-to-HIGH Transition Logic Diagram Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. ©1992 Fairchild Semiconductor Corporation 74VHC374 Rev. 1.3 Functional Description The VHC374 consists of eight edge-triggered flip-flops with individual D-type inputs and 3-STATE true outputs. ...
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... Operating Temperature OPR Input Rise and Fall Time 3.3V ± 0. 5.0V ± 0. Note: 1. Unused inputs must be held HIGH or LOW. They may not float. ©1992 Fairchild Semiconductor Corporation 74VHC374 Rev. 1.3 Parameter (1) Parameter 3 Rating –0.5V to +7.0V –0.5V to +7.0V –0. 0.5V CC –20mA ±20mA ±25mA ± ...
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... OL (2) V Quiet Output Minimum OLV Dynamic V OL (2) V Minimum HIGH Level IHD Dynamic Input Voltage (2) V Maximum LOW Level ILD Dynamic Input Voltage Note: 2. Parameter guaranteed by design. ©1992 Fairchild Semiconductor Corporation 74VHC374 Rev. 1.3 (V) Conditions Min. 1.50 0 –50µ 1 2.9 IL 4.4 = – ...
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... can be calculated by the equation Operating Requirements Symbol Parameter t (H), t (L) Minimum Pulse Width W W (CP) t Minimum Set-Up Time S t Minimum Hold Time H ©1992 Fairchild Semiconductor Corporation 74VHC374 Rev. 1.3 V (V) Conditions CC = 15pF 3.3 ± 0 50pF 15pF 5.0 ± 0 50pF 1kΩ = 15pF 3.3 ± ...
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... Physical Dimensions Dimensions are in inches (millimeters) unless otherwise noted. Figure 2. 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide ©1992 Fairchild Semiconductor Corporation 74VHC374 Rev. 1.3 Package Number M20B 6 www.fairchildsemi.com ...
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... Physical Dimensions (Continued) Dimensions are in millimeters unless otherwise noted. Figure 3. 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide ©1992 Fairchild Semiconductor Corporation 74VHC374 Rev. 1.3 Package Number M20D 7 www.fairchildsemi.com ...
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... Physical Dimensions (Continued) Dimensions are in millimeters unless otherwise noted. Figure 4. 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide ©1992 Fairchild Semiconductor Corporation 74VHC374 Rev. 1.3 Package Number MTC20 8 www.fairchildsemi.com ...
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... TRADEMARKS The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is not intended exhaustive list of all such trademarks. ® ACEx Across the board. Around the world. ActiveArray Bottomless Build it Now CoolFET CROSSVOLT CTL™ Current Transfer Logic™ ...