AD7822 Analog Devices, AD7822 Datasheet
AD7822
Specifications of AD7822
Available stocks
Related parts for AD7822
AD7822 Summary of contents
Page 1
... EOC (end of conversion) signal goes high logic low at that point, the ADC is powered down. The AD7822 and AD7825 also have a separate power-down pin (see the Operating Modes section). The parallel interface is designed to allow easy interfacing to microprocessors and DSPs ...
Page 2
... Interfacing Multiplexer Address Inputs .................................. 18 AD7822 Standalone Operation ................................................ 19 Outline Dimensions ....................................................................... 20 Ordering Guide .......................................................................... 25 Changes to Typical Connection Diagram Section........................7 Changes to Analog Input Section....................................................8 Changes to Analog Input Selection Section...................................9 Changes to Power-Up Times Section .......................................... 10 Changes to Power vs. Throughput Section ................................. 11 Added AD7822 Stand-Alone Operation section ....................... 15 12/99—Rev Rev. A Rev Page ...
Page 3
... V min 0.8 V max 2 V min 0.4 V max ±1 μA max 10 pF max Rev Page AD7822/AD7825/AD7829 Test Condition/Comment kHz MHz IN SAMPLE fa = 27.3 kHz 28.3 kHz kHz IN See Analog Input section Input voltage span = 2.5 V Default V = 1.25 V MID Input voltage span = 2 V ...
Page 4
... AD7822/AD7825/AD7829 Parameter LOGIC OUTPUTS Output High Voltage Output Low Voltage High Impedance Leakage Current High Impedance Capacitance CONVERSION RATE Track-and-Hold Acquisition Time Conversion Time POWER SUPPLY REJECTION V ± 10% DD POWER REQUIREMENTS Normal Operation Power-Down Power Dissipation ...
Page 5
... Power-up time from rising edge of CONVST using external 2.5 V reference , quoted in the timing characteristics is the true bus relinquish time 10 200µ OUTPUT PIN C L 50pF 200µ Figure 2. Load Circuit for Access Time and Bus Relinquish Time Rev Page AD7822/AD7825/AD7829 = 5 V ± 10%, and time required for an output DD 2.1V ...
Page 6
... AD7822/AD7825/AD7829 ABSOLUTE MAXIMUM RATINGS T = 25°C, unless otherwise noted. A Table 3. Parameter V to AGND DGND DD Analog Input Voltage to AGND IN1 IN8 Reference Input Voltage to AGND V Input Voltage to AGND MID Digital Input Voltage to DGND Digital Output Voltage to DGND Operating Temperature Range ...
Page 7
... The track-and-hold goes into track mode again 120 ns after the start of a conversion. The state of the CONVST signal is checked at the end of a conversion logic low, the AD7822/ AD7825/AD7829 powers down (see the Operating Modes section of the data sheet). ...
Page 8
... The AD7822/AD7825/AD7829 are tested using the CCIF standard, where two input frequencies near the top end of the input bandwidth are used. In this case, the second- and third- order terms are of different significance ...
Page 9
... Variations in power supply affect the full-scale transition but not the converter linearity. Power supply rejection is the maximum change in the full-scale transition point due to a change in power supply voltage from the nominal value. Rev Page AD7822/AD7825/AD7829 input of the AD7822/ IN before starting another IN ...
Page 10
... AD7822/AD7825/ DD AD7829 power low current mode, that is, power-down mode, with the default logic level on the EOC pin on the AD7822 and AD7825 equal to a low. Ensure the CONVST line is not floating when V is applied, because this can put the DD AD7822/AD7825/AD7829 into an unknown state ...
Page 11
... A rising edge on the CONVST pin causes the AD7829 to fully power up, while a rising edge on the PD pin causes the AD7822 and AD7825 to fully power up. For applica- tions where power consumption is of concern, the automatic power-down at the end of a conversion should be used to improve power performance (see the Power vs ...
Page 12
... V ± 2%. Analog Input Structure Figure 15 shows an equivalent circuit of the analog input structure of the AD7822/AD7825/AD7829. The two diodes, D1 and D2, provide ESD protection for the analog inputs. Care must be taken to ensure that the analog input signal never AD7822/ exceeds the supply rails by more than 200 mV ...
Page 13
... IN Figure 17. Effective Number of Bits vs. Acquisition Time for the AD7825 The on-chip track-and-hold can accommodate input frequencies to 10 MHz, making the AD7822/AD7825/AD7829 ideal for subsampling applications. When the AD7825 is converting a 10 MHz input signal at a sampling rate of 2 MSPS, the effective number of bits typically remains above seven, corresponding to a signal-to-noise ratio of 42 dBs, as shown in Figure 18 ...
Page 14
... DD CONVST Figure 20 shows how to power up the AD7822 or AD7825 when V is first connected or after the ADCs have been powered down, DD using the PD pin or the CONVST pin, with either the on-chip reference or an external reference. When the supplies are first connected or after the part has been powered down by the PD ...
Page 15
... the power-up time is 1 μs and the conversion DD time is 330 ns (@ +25°C), the AD7822 can be said to dissipate 36 mW (maximum) for 1.33 μs during each conversion cycle. If the throughput rate is 100 kSPS, the cycle time is 10 μs and the average power dissipated during each cycle is (1.33/10) × ...
Page 16
... DB0 TO DB7 The ADC is powered up again on the rising edge of the CONVST signal. Superior power performance can be achieved in this mode of operation by powering up the AD7822/AD7825/ AD7829 only to carry out a conversion. The parallel interface of the AD7822/AD7825/AD7829 remains fully operational while the ADCs are powered down. A read may occur while the part is powered down, and, therefore, it does not necessarily need to be placed within the EOC pulse, as shown in Figure 25 ...
Page 17
... RD to access the data. In systems where the part is interfaced to a gate array or ASIC, this EOC pulse can be applied to the CS and RD inputs to latch data out of the AD7822/ AD7825/AD7829 and into the gate array or ASIC. This means that the gate array or ASIC does not need any conversion status ...
Page 18
... INT 1 ADDITIONAL PINS OMITTED FOR CLARITY. Figure 27. Interfacing to the 8051 AD7822/AD7825/AD7829 TO PIC16C6x/PIC16C7x Figure 28 shows a parallel interface between the AD7822/ AD7825/AD7829 and the PIC16C64/PIC16C65/PIC16C74. The EOC signal on the AD7822/AD7825/AD7829 provides an interrupt request to the microcontroller when a conversion begins. Of the PIC16C6x/PIC16C7x range of microcontrollers, only the PIC16C64/PIC16C65/PIC16C74 can provide the option of a parallel slave port ...
Page 19
... AD7822 STANDALONE OPERATION The AD7822, being the single channel device, does not have any multiplexer addressing associated with it and can be controlled with just one signal, that is, the CONVST signal. As shown in Figure 31, the RD and CS pins are both tied to the EOC pin. ADDRESS ...
Page 20
... AD7822/AD7825/AD7829 OUTLINE DIMENSIONS PIN 1 0.210 (5.33) MAX 0.150 (3.81) 0.130 (3.30) 0.115 (2.92) 0.022 (0.56) 0.018 (0.46) 0.014 (0.36) 0.30 (0.0118) 0.10 (0.0039) COPLANARITY 0.10 1.060 (26.92) 1.030 (26.16) 0.980 (24.89 0.280 (7.11) 0.250 (6.35) 1 0.240 (6.10) 10 0.100 (2.54) BSC 0.060 (1.52) 0.015 (0.38) 0.015 (0.38) MIN GAUGE PLANE SEATING PLANE 0.005 (0.13) MIN 0.070 (1.78) 0.060 (1.52) 0.045 (1.14) COMPLIANT TO JEDEC STANDARDS MS-001-AD CONTROLLING DIMENSIONS ARE IN INCHES ...
Page 21
... PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. CORNER LEADS MAY BE CONFIGURED AS WHOLE OR HALF LEADS. Figure 35. 24-Lead Plastic Dual In-Line Package [PDIP] Narrow Body (N-24-1) Dimensions shown in inches and (millimeters) Rev Page AD7822/AD7825/AD7829 4.50 4.40 4.30 6.40 BSC 0.20 0.09 0.75 8° ...
Page 22
... AD7822/AD7825/AD7829 0.30 (0.0118) 0.10 (0.0039) COPLANARITY 0.10 0.15 0.05 15.60 (0.6142) 15.20 (0.5984 7.60 (0.2992) 7.40 (0.2913) 1 10.65 (0.4193) 12 10.00 (0.3937) 2.65 (0.1043) 2.35 (0.0925) SEATING 0.51 (0.0201) 1.27 (0.0500) 0.33 (0.0130) PLANE BSC 0.31 (0.0122) 0.20 (0.0079) COMPLIANT TO JEDEC STANDARDS MS-013-AD CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. ...
Page 23
... CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. Figure 39. 28-Lead Standard Small Outline Package [SOIC_W] Dimensions shown in millimeters and (inches) Rev Page AD7822/AD7825/AD7829 15 0.580 (14.73) 0.485 (12.31) 14 0.625 (15.88) 0.600 (15.24) ...
Page 24
... AD7822/AD7825/AD7829 PIN 1 0.15 0.05 COPLANARITY 9.80 9.70 9. 4.50 4.40 4. 0.65 BSC 1.20 MAX 0.30 0.20 SEATING 0.19 0.09 PLANE 0.10 COMPLIANT TO JEDEC STANDARDS MO-153-AE Figure 40. 28-Lead Thin Shrink Small Outline Package [TSSOP] (RU-28) Dimensions shown in millimeters Rev Page 6.40 BSC 8 ° 0.75 0 ° 0.60 0.45 ...
Page 25
... AD7822BRZ-REEL −40°C to +85°C AD7822BRZ-REEL7 1 −40°C to +85°C AD7822BRU −40°C to +85°C AD7822BRU-REEL −40°C to +85°C AD7822BRU-REEL7 −40°C to +85°C 1 AD7822BRUZ −40°C to +85°C 1 AD7822BRUZ-REEL −40°C to +85°C 1 AD7822BRUZ-REEL7 −40°C to +85°C AD7825BN − ...
Page 26
... AD7822/AD7825/AD7829 NOTES Rev Page ...
Page 27
... NOTES AD7822/AD7825/AD7829 Rev Page ...
Page 28
... AD7822/AD7825/AD7829 NOTES ©2006 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. C01321-0-8/06(C) Rev Page ...