ADV7177 Analog Devices, ADV7177 Datasheet

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... MPEG-1 and MPEG-2 Video, DVD, Digital Satellite/ Cable Systems (Set Top Boxes/IRDs), Digital TVs, CD Video/Karaoke, Video Games, PC Video/Multimedia GENERAL DESCRIPTION The ADV7177/ADV7178 is an integrated digital video encoder that converts Digital CCIR-601 4:2 16-bit component video data into a standard analog baseband television signal FUNCTIONAL BLOCK DIAGRAM ...

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... ADV7177/ADV7178–SPECIFICATIONS 5 V SPECIFICATIONS ( Parameter 3 STATIC PERFORMANCE Resolution (Each DAC) Accuracy (Each DAC) Integral Nonlinearity Differential Nonlinearity 3 DIGITAL INPUTS Input High Voltage, V INH Input Low Voltage, V INL 4 Input Current Input Current Input Capacitance DIGITAL OUTPUTS Output High Voltage, V ...

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... I = 3.2 mA SINK R = 300 , SET OUT R = 300 , R = 150 SET L COMP = 0 150 and optimum performance obtained DAC current ( 110 C. J –3– ADV7177/ADV7178 2 . All specifications unless otherwise noted.) MIN MAX Min Typ Max 9 0.5 0 2.4 0 16.5 17.35 18 ...

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... ADV7177/ADV7178–SPECIFICATIONS 5 V DYNAMIC SPECIFICATIONS Parameter Filter Characteristics 3 Luma Bandwidth (Low-Pass Filter) Stopband Cutoff Passband Cutoff Chroma Bandwidth Stopband Cutoff Passband Cutoff Luma Bandwidth (Low-Pass Filter) Stopband Cutoff Passband Cutoff Chroma Bandwidth Stopband Cutoff Passband Cutoff ...

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... PAL MODE >50 dB Attenuation >3 dB Attenuation PAL MODE >40 dB Attenuation >3 dB Attenuation Normal Power Mode Normal Power Mode RMS Peak Periodic RMS Peak Periodic NTSC NTSC PAL PAL –5– ADV7177/ADV7178 = 300 . All specifications SET MIN Min Typ Max Units 7.0 MHz 4.2 MHz 3.2 MHz 2.0 MHz 7 ...

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... ADV7177/ADV7178 5 V TIMING SPECIFICATIONS Parameter 3, 4 MPU PORT SCLOCK Frequency SCLOCK High Pulsewidth SCLOCK Low Pulsewidth Hold Time (Start Condition Setup Time (Start Condition Data Setup Time SDATA, SCLOCK Rise Time SDATA, SCLOCK Fall Time, t ...

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... REF otherwise noted.) Conditions After This Period the First Clock Is Generated Repeated for Start Condition 3 ns, measured between the 10% and 90% points. Timing reference points at 50% for inputs and –7– ADV7177/ADV7178 = 300 . All specifications SET MIN MAX Min Typ ...

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... ADV7177/ADV7178 SDATA SCLOCK CLOCK HSYNC, CONTROL FIELD/VSYNC, I/PS BLANK PIXEL INPUT DATA HSYNC, CONTROL FIELD/VSYNC, O/PS BLANK CLOCK CLOCK/2 CLOCK CLOCK/2 CLOCK OSD EN OSD0– Figure 1. MPU Port Timing Diagram Figure 2. Pixel and Control Data Timing Diagram ...

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... ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the ADV7177/ADV7178 feature proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, pr oper ESD precautions are recommended to avoid performance degradation or loss of functionality ...

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... I TTL Address Input. This signal sets up the LSB of the MPU address. G Ground Pin. I The input resets the on-chip timing generator and sets the ADV7177/ADV7178 into default mode. This is NTSC operation, Timing Slave Mode 0, 8-Bit Operation, 2 Composite and S VHS out. I MPU Port Serial Interface Clock Input. ...

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... SYNC, BLANK and Burst levels are added to the YCrCb data. Macrovision antitaping (ADV7178 only), closed captioning, OSD (ADV7177 only), and teletext levels are also added to Y, and the resultant data is interpolated to a rate of 27 MHz. The interpolated data is filtered and scaled by three digital FIR filters ...

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... ADV7177/ADV7178 0 –10 TYPE A –20 –30 –40 –50 – FREQUENCY – MHz Figure 7. NTSC Low-Pass Filter 0 –10 –20 –30 –40 –50 – FREQUENCY – MHz Figure 8. NTSC Notch Filter 0 –10 TYPE A –20 –30 –40 –50 – FREQUENCY – ...

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... OSD window can be an entire screen or just one pixel, its size may change by using the OSD_EN signal to control the width line-by-line basis. Figure 4 illustrates OSD timing on the ADV7177. SUBCARRIER RESET The ADV7177/ADV7178 can be used in subcarrier reset mode. The subcarrier will reset to Field 0 at the start of the following field when a low to high transition occurs on this input pin ...

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... Register 0 TR0 = The ADV7177/ADV7178 generates H, V and F signals required for the SAV (Start Active Video) and EAV (End Active Video) time codes in the CCIR-656 standard. The H bit is output on the HSYNC pin, the V bit is output on the BLANK pin, and the F bit is output on the FIELD/VSYNC pin ...

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... Figure 15. Timing Mode 0 (NTSC Master Mode) VERTICAL BLANK ODD FIELD VERTICAL BLANK 313 314 315 316 317 318 EVEN FIELD Figure 16. Timing Mode 0 (PAL Master Mode) –15– ADV7177/ADV7178 DISPLAY DISPLAY 283 284 285 272 273 274 DISPLAY ...

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... In this mode the ADV7177/ADV7178 accepts horizontal SYNC and Odd/Even FIELD signals. A transition of the FIELD input when HSYNC is low indicates a new frame, i.e., vertical retrace. The BLANK signal is optional. When the BLANK input is dis- abled, the ADV7177/ADV7178 automatically blanks all normally blank lines. Mode 1 is illustrated in Figure 18 (NTSC) and Figure 19 (PAL). ...

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... HSYNC is low indicates a new frame, i.e., vertical retrace. The BLANK signal is optional. When the BLANK input is disabled, the ADV7177/ADV7178 automatically blanks all normally blank lines. Pixel data is latched on the rising clock edge follow- ing the timing signal transitions. Mode 1 is illustrated in Figure 18 (NTSC) and Figure 19 (PAL). Figure 20 illustrates the HSYNC, BLANK and FIELD for an odd or even field transition relative to the pixel data ...

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... Register 0 TR0 = this mode the ADV7177/ADV7178 accepts horizontal and vertical SYNC signals. A coincident low transition of both HSYNC and VSYNC inputs indicates the start of an odd field. A VSYNC low transition when HSYNC is high indicates the start of an even field. ...

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... HSYNC and VSYNC inputs indicates the start of an Odd Field. A VSYNC low transition when HSYNC is high indicates the start of an even field. The BLANK signal is optional. When the BLANK input is disabled, the ADV7177/ADV7178 automatically blanks all normally blank lines as per CCIR-624. Mode 2 is illustrated in Figure 21 (NTSC) and Figure 22 (PAL). Figure 23 illus- trates the HSYNC, BLANK and VSYNC for an even-to-odd field transition relative to the pixel data ...

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... In this mode, the ADV7177/ADV7178 accepts or generates Horizontal SYNC and Odd/Even FIELD signals. A transition of the FIELD input when HSYNC is high indicates a new frame, i.e., vertical retrace. The BLANK signal is optional. When the BLANK input is disabled, the ADV7177/ADV7178 automatically blanks all normally blank lines as per CCIR-624. Mode 3 is illustrated in Figure 25 (NTSC) and Figure 26 (PAL). ...

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... Figure 28. The LSB sets either a read or write operation. Logic Level “1” corresponds to a read operation, while Logic Level “0” corresponds to a write operation set by setting the ALSB pin of the ADV7177/ADV7178 to Logic Level “0” or Logic Level “1.” 0 ...

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... START ADDR R/W ACK SUBADDRESS ACK Figure 30 shows bus write and read sequences. REGISTER ACCESSES The MPU can write to or read from all of the ADV7177/ ADV7178 registers except the subaddress register, which is a write-only register. The subaddress register determines which register the next read or write operation accesses. All communi- cations with the part through the bus start with an access to the subaddress register ...

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... THIS BIT REV. 0 MR0 BIT DESCRIPTION Encode Mode Control (MR01–MR00) These bits are used to set up the encode mode. The ADV7177/ ADV7178 can be set up to output NTSC, PAL ( and PAL (M) standard video. Pedestal Control (MR02) This bit specifies whether a pedestal generated on the NTSC composite video signal ...

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... DAC Control (MR15–MR13) These bits can be used to power down the DACs. This can be used to reduce the power consumption of the ADV7177/ ADV7178 if any of the DACs are not required in the application. Color Bar Control (MR17) This bit can be used to generate and output an internal color bar test pattern ...

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... T PCLK PCLK PCLK 1 1 128 x T PCLK LINE Figure 38. Timing Register 1 –25– ADV7177/ADV7178 TR01 TR02 TR00 MASTER/SLAVE CONTROL TR00 0 SLAVE TIMING 1 MASTER TIMING SELECTION 0 MODE 0 1 MODE 1 0 MODE 2 1 MODE 3 CED15 CED14 ...

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... RED Component Video (For RGB Mode) G: GREEN Component Video (For RGB Mode) B: BLUE Component Video (For RGB Mode) Low Power Control (MR27) This bit enables the lower power mode of the ADV7177/ ADV7178. This will reduce DAC current by 50%. MR26 MR25 MR24 MR23 ...

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... OUTPUT 1 ENABLE 1 1 CLOCK OUTPUT OFF MR34 ZERO SHOULD BE WRITTEN TO INPUT COLOR THIS BIT BLACK Figure 41. Mode Register 3 Y0 Cb0 Cr1 Cr7 Figure 42. OSD Registers –27– ADV7177/ADV7178 , 0 [ 0].) MR31 ...

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... The “Recommended Analog Circuit Layout” shows the analog interface between the device and monitor. The layout should be optimized for lowest noise on the ADV7177/ ADV7178 power and ground lines by shielding the digital inputs and providing good decoupling. The lead length between groups ...

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... RESET 44 CLOCK SCLOCK 23 43 CLOCK SDATA 24 2 CLOCK SET ALSB GND 18 19 29, 42 10k Figure 43. Recommended Analog Circuit Layout –29– ADV7177/ADV7178 0. + (FERRITE BEAD + + 100 MPU BUS 100 ...

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... Line 284. The data for this operation is stored in closed captioning extended Data Registers 0 and 1. All clock run-in signals and timing to support closed captioning on Lines 21 and 284 are generated automatically by the ADV7177/ ADV7178. All pixels inputs are ignored during Lines 21 and 284. ...

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... APPENDIX 3 NTSC WAVEFORMS (WITH PEDESTAL) Figure 45. NTSC Composite Video Levels Figure 46. NTSC Luma Video Levels 835mV (pk-pk) Figure 47. NTSC Chroma Video Levels Figure 48. NTSC RGB Video Levels –31– ADV7177/ADV7178 1268.1mV PEAK COMPOSITE 1048.4mV REF WHITE 714.2mV BLACK LEVEL 387.6mV BLANK LEVEL 334 ...

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... ADV7177/ADV7178 130.8 IRE 100 IRE 0 IRE –40 IRE 100 IRE 0 IRE –40 IRE 1101.6mV 307mV (pk-pk) 650mV 198.4mV 0mV 100 IRE 0 IRE –40 IRE NTSC WAVEFORMS (WITHOUT PEDESTAL) Figure 49. NTSC Composite Video Levels Figure 50. NTSC Luma Video Levels Figure 51. NTSC Chroma Video Levels Figure 52. NTSC RGB Video Levels – ...

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... REV. 0 PAL WAVEFORMS Figure 53. PAL Composite Video Levels Figure 54. PAL Luma Video Levels 885mV (pk-pk) Figure 55. PAL Chroma Video Levels Figure 56. PAL RGB Video Levels –33– ADV7177/ADV7178 PEAK COMPOSITE REF WHITE 696.4mV BLANK/BLACK LEVEL SYNC LEVEL REF WHITE 696.4mV BLANK/BLACK LEVEL ...

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... ADV7177/ADV7178 334mV 171mV BETACAM LEVEL 0mV 334mV 505mV Figure 57. NTSC 100% Color Bars No Pedestal U Levels 309mV 158mV BETACAM LEVEL 0mV –158mV –309mV –467mV Figure 58. NTSC 100% Color Bars with Pedestal U Levels 232mV 118mV SMPTE LEVEL 0mV –118mV –232mV –350mV Figure 59. PAL 1005 Color Bars U Levels ...

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... The ADV7177/ADV7178 registers can be set depending on the user standard required. The following examples give the various register formats for several video standards. In each case the output is set to composite o/p with all DACs powered up and with the BLANK input control disabled. Addi- tionally, the burst and color information are enabled on the output and the internal color bar generator is switched off ...

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... RGB outputs of the ADV7177/ADV7178, the following filter in Figure 63 can be used. Plots of the filter characteristics are shown in Figures 64, 65 and 66. An output filter is not required if the outputs of the ADV7177/ADV7178 are connected to an analog monitor or an analog TV; however, if the output signals are applied to a system where sampling is used (e.g., digital TV), a filter is required to prevent aliasing ...

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... For external buffering of the ADV7177/ADV7178 DAC out- puts, the configuration in Figure 67 is recommended. This configuration shows the DAC outputs running at half (18 mA) their full current (34.7 mA) capability. This will allow the ADV7177/ADV7178 to dissipate less power, the analog current is reduced by 50% with 300 and a R SET mode is recommended for 3 ...

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... ADV7177/ADV7178 OUTLINE DIMENSIONS Dimensions shown in inches and (mm). Plastic Quad Flatpack (S-44) 0.548 (13.925) 0.546 (13.875) 0.096 (2.44) 0.398 (10.11) MAX 0.390 (9.91) 0.037 (0.94) 8 0.025 (0.64) 33 0.8 34 SEATING PLANE TOP VIEW (PINS DOWN 0.040 (1.02) 0.040 (1.02) 0.032 (0.81) 0.032 (0.81) 0.033 (0.84) 0.083 (2.11) 0.029 (0.74) 0.077 (1.96) –38– 0.016 (0.41) ...