DS99R124Q-EVK/NOPB National Semiconductor, DS99R124Q-EVK/NOPB Datasheet
DS99R124Q-EVK/NOPB
Specifications of DS99R124Q-EVK/NOPB
Related parts for DS99R124Q-EVK/NOPB
DS99R124Q-EVK/NOPB Summary of contents
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... With fewer wires to the physical interface of the display, FPD- Link output with LVDS technology is ideal for high speed, low power and low EMI data transfer. The DS99R124Q is offered in a 48-pin LLP package and is specified over the automotive AEC-Q100 Grade 2 tempera- ture range of -40˚C to +105˚C. ...
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... TxCLKOUT LVDS TxCLKOUT LVDS www.national.com FPD-Link II to FPD-Link Convertor - DS99R124Q Description True input The input must be AC coupled with a 100 nF capacitor. Internal termination. Inverting input The input must be AC coupled with a 100 nF capacitor. Internal termination. Common-Mode Filter VCM center-tap is a virtual ground which maybe ac-coupled to ground to increase receiver common mode noise immunity. Recommended value is 4.7 μ ...
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Pin Name Pin # I/O, Type LVCMOS Outputs OS[2:0] 10, 11 LVMOS LOCK 27 O, LVMOS Control and Configuration PDB 1 I, LVCMOS w/ pull-down VODSEL 33 I, LVCMOS w/ pull-down OEN 34 I, LVCMOS w/ pull-down OSS_SEL ...
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... LLP, 7.0 X 7.0 X 0.8 mm, 0.5 mm pitch DS99R124QSQ 48–pin LLP, 7.0 X 7.0 X 0.8 mm, 0.5 mm pitch DS99R124QSQX 48–pin LLP, 7.0 X 7.0 X 0.8 mm, 0.5 mm pitch Note: Automotive Grade (Q) product incorporates enhanced manufacturing and support processes for the automotive market, including defect detection methodologies. Reliability qualification is compliant with the requirements and temperature grades defined in the AEC Q100 standard ...
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... Absolute Maximum Ratings If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Supply Voltage – V (1.8V) DDn Supply Voltage – V (3.3V) DDTX Supply Voltage – V DDIO LVCMOS I/O Voltage −0.3V to +(VDDIO + 0.3V) Receiver Input Voltage LVDS Output Voltage − ...
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Symbol Parameter V High Level Output Voltage OH V Low Level Output Voltage OL I Output Short Circuit Current OS I TRI-STATE ® Output Current OZ 1.8 V I/O LVCMOS DC SPECIFICATIONS – High Level Input Voltage IH ...
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Switching Characteristics Over recommended operating supply and temperature ranges unless otherwise specified. Symbol Parameter FPD-Link II t Lock Time DDLT (Note 5) t Input Jitter Tolerance DJIT FPD-Link Output t Low to High Transition Time TLHT t High to Low ...
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Recommended Timing for the Serial Control Bus Over recommended operating supply and temperature ranges unless otherwise specified. Symbol Parameter f SCL Clock Frequency SCL t SCL Low Period LOW t SCL High Period HIGH t Hold time for a start ...
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Note 1: “Absolute Maximum Ratings” indicate limits beyond which damage to the device may occur, including inoperability and degradation of device reliability and/or performance. Functional operation of the device and/or non-degradation at the Absolute Maximum Ratings or other conditions beyond ...
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FIGURE 3. FPD-Link & LVCMOS Powerdown Delay FIGURE 4. FPD-Link Outputs Enable Delay FIGURE 5. Deserializer PLL Lock Times 10 30105288 30105289 30105214 ...
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FIGURE 6. FPD-Link (LVDS) Single-ended and Differential Waveforms FIGURE 7. FPD-Link Transmitter Pulse Positions FIGURE 8. Receiver Input Jitter Tolerance 11 30105206 30105217 30105216 www.national.com ...
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Typical Performance Characteristics FIGURE 11. Typical Input Jitter Tolerance Curve at 43 MHz www.national.com FIGURE 9. BIST PASS Waveform FIGURE 10. Serial Control Bus Timing Diagram 12 30105252 30105236 30105291 ...
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FIGURE 12. Typical Total IDD Current (1.8V Supply Function of PCLK FIGURE 13. Typical IDDTX Current (3.3V Supply function of PCLK 13 30105292 30105293 www.national.com ...
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... Functional Description The DS99R124Q receives 24-bits of data over a single serial FPD-Link II pair operating at 140Mbps to 1.2Gbps. The serial stream also contains an embedded clock, and the DC-bal- ance information which enhances signal quality and supports AC coupling. The receiver copnverts the serial stream into a 4-channel (3 data and 1 clock) FPD-Link LVDS Interface ...
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If there is a loss of clock from the input serial stream, LOCK is driven Low and the state of the outputs are based on the OSS_SEL setting (configuration pin or register). INPUTS PDB OEN OSS_SEL ...
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TABLE 3. SSCG Configuration (LFMODE = L) — Des Output SSC[2:0] Inputs LFMODE = L ( MHz) SSC2 SSC1 TABLE 4. SSCG Configuration (LFMODE = H) ...
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... Des detects the BIST mode pattern and command (DCA and DCB code) the RGB and control signal outputs are shut off. Step 2: Place the DS99R124Q Des in BIST mode by setting the BISTEN = H. The Des is now in the BIST mode. If BISTM = H, the Des will check the incoming serial payloads for errors. ...
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... Repeated Start condition. All communication on the bus ends with a Stop condition. A READ is shown in 30105241 and a WRITE is shown in If the Serial Bus is not required, the three pins may be left open (NC). TABLE 5. ID[x] Resistor Value – DS99R124Q Des Resistor )) with a 10 DDIO RID kΩ 1.8V, NOT ...
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... TABLE 6. DS99R124Q — Serial Bus Control Registers ADD ADD Register Name Bit(s) (dec) (hex Des Config 3 Slave Des Features 5:4 3 2:0 R/W Defa Function Description ult (bin) R/W 0 LFMODE SSCG Mode – low frequency support MHz Operation MHz Operation R/W ...
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ADD ADD Register Name Bit(s) (dec) (hex Des Features 2 7:5 2:0 www.national.com R/W Defa Function ult (bin) R/W 000 EQ Gain 4 R Enable 3 R/W 0 Reserved R/W 000 SSC 20 Description 000: ~1.625 ...
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... RGB666 application, 18 color bits (R[5:0], G[5:0], B[5:0]), Pix- el Clock (PCLK) and three control bits (VS, HS and DE) are supported across the serial link with PCLK rates from 5 to 43MHz. FIGURE 23. DS99R124Q Typical Connection Diagram — Pin Control TYPICAL APPLICATION CONNECTION Figure 23 shows a typical application of the DS99R124QQ Des in pin mode for a 43 MHz WVGA Display Application ...
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... LIVE LINK INSERTION The Ser and Des devices support live pluggable applications. The automatic receiver lock to random data “plug & go” hot insertion capability allows the DS99R124Q to attain lock to the active data stream during a live insertion event. PCB LAYOUT AND POWER SYSTEM CONSIDERATIONS ...
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Physical Dimensions inches (millimeters) unless otherwise noted 48–pin LLP Package (7 7 0.8 mm, 0.5 mm pitch) NS Package Number SQA48A 23 www.national.com ...
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... For more National Semiconductor product information and proven design tools, visit the following Web sites at: www.national.com Products Amplifiers www.national.com/amplifiers Audio www.national.com/audio Clock and Timing www.national.com/timing Data Converters www.national.com/adc Interface www.national.com/interface LVDS www.national.com/lvds Power Management www.national.com/power Switching Regulators www.national.com/switchers LDOs www.national.com/ldo LED Lighting www ...