LTC1852 LINER [Linear Technology], LTC1852 Datasheet
LTC1852
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LTC1852 Summary of contents
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... UNI/BIP 0.5 PGA BUSY 0 DIFF /S6 OUT A2 /S5 OUT A1 /S4 OUT A0 /S3 OUT D11/S2 D10/S1 –0.5 D9/S0 DATA OUTPUT D8 LATCHES DRIVERS –1 OGND 18523 BD LTC1852/LTC1853 Integral Linearity 512 1024 1536 2048 2560 3072 3584 4096 CODE 1852 F01 18523fa 1 ...
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... For more information on tape and reel specifi cations (Note Ambient Operating Temperature Range + 0.3V) LTC1852C/LTC1853C .............................. 0°C to 70°C DD LTC1852I/LTC1853I ............................. –40°C to 85°C + 0.3V) Storage Temperature Range ...................–65°C to 150°C DD Lead Temperature (Soldering, 10 sec) ................. 300°C LTC1853 48 ...
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... During Conversions ) ACQ 25°C. (Notes 5) A CONDITIONS 40kHz Input Signal 40kHz Input Signal, First 5 Harmonics 40kHz Input Signal LTC1852/LTC1853 (Notes 5,6) DD LTC1852 LTC1853 TYP MAX MIN TYP MAX 12 ±0.25 ±1 ±0.35 ±1 ±0.25 ±1 ±0.25 ±1 ±0.5 ±2 ±1 ± ...
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... LTC1852/LTC1853 INTERNAL REFERENCE PARAMETER REFOUT Output Voltage REFOUT Output Temperature Coeffi cient REFOUT Line Regulation Reference Buffer Gain REFCOMP Output Voltage REFCOMP Impedance DIGITAL INPUTS AND DIGITAL OUTPUTS operating temperature range, otherwise specifi cations are at T SYMBOL PARAMETER V High Level Input Voltage ...
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... Nap Mode (Note 10) Sleep Mode (Note 10) (Notes 10, 11 25pF L (Note 10 25pF 100pF L 0°C to 70°C – 40°C to 85°C LTC1852/LTC1853 MIN TYP MAX UNITS ● 2.7 5.5 ● 2.7 5.5 ● ● 0.83 1.33 ● ● ...
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... Note 8: Bipolar offset is the offset voltage measured from – 0.5LSB when the output code fl ickers between 1111 1111 1111 and 0000 0000 0000. For the LTC1853 and between 11 1111 1111 and 00 0000 0000 for the LTC1852. , Note 9: Guaranteed by design, not subject to test. ...
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... The output swings between OV and OGND. DD D7/S0 (Pin 23, LTC1852): Three-State Digital Data Outputs. Active when RD is low. Following a conversion, bit 7 of the present conversion is available on this pin. In Readback mode, the end of sequence bit of the current sequencer location (S0) is available on this pin. The output swings between OV and OGND ...
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... Data Outputs. Active when RD is low. The outputs swing between OV and OGND (Pins 31 to 32, LTC1852): No Connect. There is no internal connection to these pins. BUSY (Pin 33): Converter Busy Output. The BUSY output has two functions. At the start of a conversion, BUSY will go low and remain low until the conversion is completed. ...
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... D11/S2 (LTC1853) Data Output 22 D8/S1 (LTC1852) Data Output 22 D10/S1 (LTC1853) Data Output 23 D7/S0 (LTC1852) Data Output 23 D9/S0 (LTC1853) Data Output (LTC1852) Data Outputs (LTC1853) Data Outputs (LTC1852) No Connect BUSY 33 Converter Busy Output 34 OGND Output Ground 35 OV ...
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... LTC1852/LTC1853 APPLICATIONS INFORMATION The LTC1852/LTC1853 are complete and very fl exible data acquisition systems. They consist of a 10-bit/12-bit, 400ksps capacitive successive approximation A/D con- verter with a wideband sample-and-hold, a confi gurable 8-channel analog input multiplexer, an internal reference and reference buffer amplifi er, a 16-bit parallel digital output and digital control logic, including a programmable sequencer ...
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... The full-linear bandwidth is the input frequency at which the S/( has dropped to 68dB for the LTC1853 (11 effective bits) or 56dB for the LTC1852 (9 effective bits). The LTC1852/LTC1853 have been designed to optimize input bandwidth, allowing the ADC to undersample input signals with frequencies above the converter’s Nyquist fre- quency. The noise fl ...
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... Driving the Analog Inputs The inputs of the LTC1852/LTC1853 are easy to drive. Each of the analog inputs can be used as a single-ended input relative to the input common pin (CH0-COM, CH1-COM, etc pairs (CH0 and CH1, CH2 and CH3, CH4 and CH5, CH6 and CH7) for differential inputs. Regardless of the MUX confi ...
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... The noise and the distortion of the input amplifi er and other circuitry must be considered since they will add to the LTC1852/LTC1853 noise and distortion. Noisy input circuitry should be fi ltered prior to the analog inputs to minimize noise. A simple 1-pole RC fi lter is suffi cient for many applications. For instance, a 200Ω ...
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... FS – 1.5LSB, FS – 0.5LSB). The three most signifi cant bits of the data word (D11, D10 and D9 for the LTC1853; D9, D8 and D7 for the LTC1852) 14 also function as output bits when reading the contents of the programmable sequencer ...
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... APPLICATIONS INFORMATION BOARD LAYOUT AND BYPASSING To obtain the best performance from the LTC1852/LTC1853, a printed circuit board with ground plane is required. The ground plane under the ADC area should be as free of breaks and holes as possible, such that a low impedance path between all ADC grounds and all ADC decoupling capacitors is provided ...
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... RD Figure CONVST and RD Setup Timing Power Shutdown The LTC1852/LTC1853 provide two power shutdown modes, Nap and Sleep, to save power during inactive periods. The Nap mode reduces the power to 2.5mW and leaves only the digital logic and reference powered up. ...
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... CONV DATA (N – 1) DATA N Figure 8. Slow Memory Mode Timing CONV DATA (N – 1) Figure 9. ROM Mode Timing LTC1852/LTC1853 t 6 DATA N 18523 F06 18523 F07 DATA N DATA ( 18523 F08 DATA N 18523 F09 18523fa 17 ...
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... OUT OUT the conversion result. Program/Readback Mode The LTC1852 and LTC1853 include a sequencer that can be programmed to run a sequence locations containing a MUX address and input confi guration. The MUX address and input confi guration for each location are programmed using the DIFF , A2 to A0, UNI/BIP and PGA pins and are stored in memory along with an end-of- sequence (EOS) bit that is generated automatically ...
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... OUT (LTC1853) or DIFF /S6, A2 /S5, A1 OUT OUT D9/S2, D8/S1 and D7/S0 pins (LTC1852). The (LTC1853 (LTC1852) data output pins will remain high impedance during readback. RD going high will return the data output pins to a high impedance state Table 5 WR OPERATION MODE ...
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... LTC1852/LTC1853 APPLICATIONS INFORMATION 20 18523fa ...
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... APPLICATIONS INFORMATION LTC1852/LTC1853 18523fa 21 ...
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... LTC1852/LTC1853 TYPICAL APPLICATIONS LTC1853 Hardwired for 8-Channel Single-Ended Scan with Unipolar 0V to 4.096V Operation V 1 CH0 2 CH1 3 CH2 4 CH3 INPUT CONFIGURATION: ALL 8 CHANNELS 8-CHANNEL 5 CH4 SINGLE ENDED MULTIPLEXER TO COM 6 CH5 CH0–CH7 4.096V 7 CH6 8 CH7 9 COM 2.5V 10 REFOUT 2.5V REFERENCE 1μF 11 REFIN REF AMP 4 ...
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... BSC 6.0 – 6.2** 0.25 (.236 – .244) REF 0° – 8° -C- 0.50 0.45 – 0.75 (.0197) (.018 – .029) BSC LTC1852/LTC1853 SHDN CONVST CONTROL LOGIC CONVERT WR AND ...
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... LTC1852/LTC1853 TYPICAL APPLICATION Data buffering using two IDT7202LA15 1k x 9-bit FIFOs allows rapid collection of 1024 samples and simple interface to low power, low speed, 8-bit microcontrollers. Data and channel information are clocked in simultaneously and read out as two bytes using READ HIGH FIFO and READ LOW FIFO lines ...