LTC4258 LINER [Linear Technology], LTC4258 Datasheet
LTC4258
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LTC4258 Summary of contents
Page 1
... Sourcing Equipment (PSE). It consists of four independent ports, each with output current limit, short-circuit protec- tion, complete Powered Device (PD) detection and classi- fication capability, and programmable PD disconnect using sensing. Used with power MOSFETs and passives as in Figure 1, the LTC4258 can implement a complete IEEE 802.3af-compliant PSE ...
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... Open Circuit, Measured at DETECT n Pin 0mA < I < 31mA CLASS Into Short (V = 0V) DETECT U W ORDER PART TOP VIEW NUMBER BYP 2 35 AUTO INT 3 34 OUT1 LTC4258CGW SCL 4 33 GATE1 5 SENSE1 32 6 OUT2 GATE2 AD3 8 29 SENSE2 AD2 AD1 ...
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... Time to Measure PD Signature Resistance (Figure 2) From Successful Detect in Auto or Semiauto Mode to Class Complete From Classify Command in Manual (Figure 2) From Valid Detect to Port On in Auto Mode (Figure 2) From Port On Command to GATE Pin Current = I (Note 8) LTC4258 = 3.3V –48V unless otherwise noted DD EE MIN TYP MAX 5 ...
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... Figure 5 (Notes 8, 9) Figure 5 (Notes 8, 9) (Notes 8, 9, 10) (Notes 8, 9, 10) (Notes 8, 9) Note 6: The LTC4258 is designed to maintain a port voltage of –46.6V to –57V and the V supply voltage range accounts for the drop across the EE diode, MOSFET and sense resistor. Note 7: The LTC4258 implements overload current detection per IEEE 802.3af. The minimum overload current (I voltage ...
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... SENSE n V MIN INT t t VMIN DIS Figure 4. DC Disconnect Timing Figure Interface Timing LTC4258 PORT V T TURN ON (AUTO MODE) 4258 F02 t CLASS , t ICUT 4258 F03 4258 F04 t 8 4258 F05 4258p 5 ...
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... LTC4258 DIAGRA S SCL SDA AD3 AD2 AD1 AD0 START BY MASTER FRAME 1 SERIAL BUS ADDRESS BYTE SCL SDA AD3 AD2 AD1 AD0 R/W ACK START BY ACK BY MASTER SLAVE FRAME 1 SERIAL BUS ADDRESS BYTE SCL SDA SCL SDA ...
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... CTIO S RESET (Pin 1): Chip Reset, Active Low. When the RESET pin is low, the LTC4258 is held inactive with all ports off and all internal registers reset to their power-up states. When RESET is pulled high, the LTC4258 begins normal operation. RESET can be connected to an external capaci- tor or RC network to provide a power turn-on delay ...
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... GATE1 (Pin 33): Port 1 Gate Drive. See GATE 4. OUT1 (Pin 34): Port 1 Output Voltage Monitor. See OUT4. AUTO (Pin 35): Auto Mode Input. Auto mode is intended to allow the LTC4258 to detect and power even if there is no host controller present on the I voltage of the AUTO pin determines the state of the or t event ...
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... W TABLE 1. REGISTER AP LTC4258 4258p 9 ...
Page 10
... UVLO level (typically –28V). Bit 5 signals that the V has dropped below the V UVLO threshold. Bit 7 indicates DD that the LTC4258 die temperature has exceeded its thermal shutdown limit (see Note 4 under Electrical Characteris- tics). The logical OR of bits 4, 5 and 7 appears in the Inter- Event Register, Read ...
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... Operating Mode (Address 12h): Operating Mode Configu- ration, Read/Write. This register contains the mode bits for each of the four ports in the LTC4258. See Table 1 for mode bit encoding. At power-up, all bits in this register will be set to the logic state of the AUTO pin (Pin 35). See Operating Modes in the Applications Information section ...
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... DC disconnect timing. Misc Config (Address 17h): Miscellaneous Configuration, Read/Write. Setting bit 7 enables the INT pin. If this bit is reset, the LTC4258 will not pull down the INT pin in any condition nor will it respond to the Alert Response Address. This bit is set by default. Pushbutton Registers Note Regarding Pushbutton Registers: “ ...
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... RJ45 0.05 F MAX SPARE PAIR DATA PAIR DATA PAIR SMAJ58A 58V SPARE PAIR Figure 10. System Diagram LTC4258 PD 1N4002 SMAJ58A Rx IN 300 F 58V 0 1N4002 4 GND R PWRGD CLASS LTC4257 –48V –48V IN OUT DC/DC + CONVERTER V OUT – ...
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... Table 1. Several of the registers assume different states based on the state of the AUTO pin at reset. The default states with AUTO high allow the LTC4258 to detect and power Automatic mode, even if nothing is connected to the I interface ...
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... W U The LTC4258 will not report Detect Good if the PD has more than parallel with its signature resistor. The port’s operating mode controls if and when the LTC4258 runs a detection cycle. In manual mode, the port will sit idle until a Restart Detection (register 18h) com- mand is received ...
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... F13 maintain consistency with the standard, the I is used when referring to an initial t When the LTC4258 turns on a port, it turns on the MOSFET by pulling up on the gate. The LTC4258 is designed to power up the port in current limit, limiting the inrush current to I ...
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... The port will not repower until after the t returns to zero. In manual and semiauto modes the power enable command must be received after the t ICUT . LIM reaches zero. In auto mode the LTC4258 must complete a valid detection cycle after the t t Timing START To distinguish between normal turn-on current limit be- ...
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... By keeping track faults, the host controller can delay turning on the ICUT port again after one of these faults even if the LTC4258 reports a Detect Good. In this way the host controller implements a MOSFET cooling off period which may be programmed to protect smaller MOSFETs from repeated thermal cycling ...
Page 19
... LTC4258 to normal operating mode. A substantial transient surge suppressor can typically protect the LTC4258 and the rest of the PSE from these faults. Placing a polyfuse between the RJ-45 connector and the LTC4258 and its associated circuitry can provide additional protection. To meet safety requirements, place the polyfuse in the ground leg of the PSE’ ...
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... AD3-AD0. All LTC4258s also respond to the address (0110000)b, allowing the host to write the same command into all of the LTC4258s on a bus in a single transaction. If the LTC4258 is asserting (pulling low) the INT pin, it will also acknowledge the Alert Response Address (0001100)b using the receive byte protocol ...
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... SCL SDAIN SDAOUT AD0 LTC4258 AD1 AD2 AD3 DGND AGND BYP 0.1 F • 0.1 F • • INT SCL SDAIN SDAOUT AD0 LTC4258 AD1 AD2 AD3 DGND AGND BYP 0 INT SCL SDAIN SDAOUT AD0 LTC4258 AD1 AD2 AD3 DGND AGND BYP ...
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... LTC4258 initiated the interrupt. The master initiates the ARA procedure with a START condition and the 7-bit ARA bus address (0001100)b followed by the Read Bit (Rd LTC4258 is asserting the INT pin, it acknowledges and sends its 7-bit bus address (010A ...
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... LTC4258 to pull the INT pin down must be removed before the LTC4258 will be able to pull INT down again. This can be done by reading and clearing the event registers or by writing a 1 into the Clear All Interrupts bit (bit 7 of register 1Ah) ...
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... LTC4258 in a PSE does not guarantee 802.3af compliance. Using an LTC4258 does get you most of the way there. This section ® 1619 to control discusses the rest of the elements that go along with the LTC4258 to make an 802 ...
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... PSE to be noncompliant. For further assistance please contact Linear Technology’s Applications department. Sense Resistors The LTC4258 is designed to use a 0.5 sense resistor monitor the current through each port. The value of the sense resistor has been minimized in order to reduce power loss and as a consequence, the voltage which the LTC4258 must measure is small ...
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... Because the specifica- tion also requires the PSE to supply 400mA duty cycle, the V few percent more than the maximum total power the PSE will supply to PDs. Finally, the LTC4258s draw current DD from V EE power divided by the switcher efficiency must also be ...
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... DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED 0.152mm (0.006") PER SIDE ** DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD FLASH SHALL NOT EXCEED 0.254mm (0.010") PER SIDE LTC4258 15.290 – 15.544* (.602 – .612) 10.160 – 10.414 (.400 – .410) 2.286 – ...
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... Quad IEEE 802.3af Power Over Ethernet Controller Linear Technology Corporation 28 1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408) 432-1900 FAX: (408) 434-0507 ISOLATED 3.3V 0.1 F DGND AGND DETECT SCL 1/4 SDAIN LTC4258 SDAOUT INT V SENSE GATE OUT 0.5 Q1 –48V IRFM120A ISOLATED U3 200 ...