MB86291A Fujitsu Media Devices Limited, MB86291A Datasheet
MB86291A
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MB86291A Summary of contents
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... Graphics Display Controller MB86291A DESCRIPTION The MB86291A is an evolved version of the Fujitsu MB86290A graphics controller designed for use in a car navigation system or amusement equipment. The MB86291A is a graphics display controller with a geometry processor, digital video capture facility, and on-chip SDRAM. Embedding SDRAM implements data transfer at a higher bandwidth, resulting in faster drawing. Integrating the geometry processor reduces the CPU load, thereby improving the performance of the entire system ...
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... MB86291A (Continued) • Drawing features: Drawing at a peak rate of 800 Mpixels per second (at an internal operating frequency of 100 MHz) 2D drawing functions: Point, line, triangle, polygon, BLT, and pattern drawing 3D drawing functions: Point, line, and triangle drawing, and hidden surface removal by Z-buffering ...
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... Ground : 3.3 V power supply : 2.5 V power supply : Analog power supply : PLL power supply : Internal DRAM power supply : Do not connect anything. : Input the low level. : Input the high level. : Input the high level. MB86291A www.DataSheet4U.com 156 ACOMPR 155 VREF 154 VRO 153 AVD3 152 ...
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... DRACK DTACK INT MODE0- MODE2 TESTL, TESTH CLK S CKM Clock CLKSEL0- CLKSEL1 OSCOUT OSCCNT 4 DCLKO DCLKI AOUTR, AOUTG, AOUTB HSYNC VSYNC CSYNC EO GV VREF MB86291A VRO Graphics Controller ACOMPR, ACOMPG, ACOMPB R0-R7 HQFP208 G0-G7 B0-B7 CCLK VI0-VI7 www.DataSheet4U.com Vide output interface Vide capture interface ...
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... Input TESTH0 to TESTH5 Note : The host interface can connect the MB86291A to the SH4 (SH7750) or SH3 (SH7709) from Hitachi Ltd. the V832 from NEC the SPARClite (MB86833) from Fujitsu without any external circuit in between. (Using the SRAM interface allows the MB86291A to use another CPU.) The host CPU is set by the MODE0 and MODE1 pins as shown below ...
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... MB86291A Notes : The host interface transfers data signals at a fixed width of 32 bits. There are 23 lines for address signals handled in double words ( space. The external bus can be used at an operating frequency of 100 MHz maximum. The RDY signal at the low level sets the ready state in the SH4 or V832 mode; the signal at the low level sets the wait state in the SH3 mode ...
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... Connect the VRO pin to the analog ground with a 2.7 k resistor. For noninterlaced display in external synchronization mode, input "0" to the EO pin, for example, using a pull-down resistor. The GV signal serves to switch between graphics and video for chroma keying. The pin outputs a low level signal to select video. MB86291A www.DataSheet4U.com 7 ...
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... MB86291A Video Capture Interface Pin Name Input/output CCLK Input VI0-VI7 Input Note : The video capture interface inputs digital video signals in the ITU-RBT-656 format. Clock Input Pin Name Input/output CLK Input S Input CKM Input CLKSEL1, CLKSEL0 Input 1 OSCOUT* Input/output OSCCNT* 2 Input * not connect anything. ...
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... BLOCK DIAGRAM D0-D31 Host Interface A2-A24 Memory Interface Controller External Video Interface Controller Display Controller DAC 2D/3D Geometry Rendering Engine Engine Embedded SDRAM MB86291A www.DataSheet4U.com RBT656 DRGB ARGB 9 ...
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... FUNCTION BLOCKS Host Interfacee This block allows the MB86291A to be connected to the SH3 or SH4 microprocessor from Hitachi Ltd., the V83x microprocessor from NEC the SPARCLite from Fujitsu without any external circuit in between. The block provides an interface to transfer display list and texture pattern data directly from main memory to this device’s graphics memory or internal register using the external DMA controller ...
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... DDH V 0 POW 30* 2 Tstg 55 Symbol Min 2.3 DDL V 3.0 DDH 1.05 REF R VRO R AOUT C ACOMP MB86291A www.DataSheet4U.com Unit Max 3.0 V 4.0 V 0.5 ( 4.0) V DDH 85* 2 125 C Value Unit Typ Max 2.5 2.7 V 3.3 3 0.3 V DDH 0.8 V 1.10 1. ...
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... MB86291A Notes : The VDDL and VDDH power supplies can be turned on or off in either order. Note, however, that the VDDH voltage must not be applied alone continuously for several seconds. After turning the power on, input a pulse remaining at low level for at least 500 ns to the S pin. Then, set the S pin to high level and input the RESET signal held at low level for at least 300 s ...
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... Symbol Min V V 0.2 OH DDH V 0 4.0 OHM 8.0 OHH 4.0 OLM 8.0 OLH 9.90 I AOUT 0 V 0.1 AOUT 1. REF R ) 25.575) REF VRO MB86291A www.DataSheet4U.com 0 Value Unit Typ Max V V DDH 0 10.42 10. 1 2.7 k VRO 13 ...
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... MB86291A 2. AC Characteristics Input measurement conditions V IH 80% Input 20 tr Input measurement standard : (VIH Output measurement conditions V IH Input Output Output Output 3 Output measurement standard : VIL pHL ...
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... DAKS t 0 DAKH t 3 DRKS t 0 DRKH t 3.0 RDDZ t *2 4.5 RDD t 2.5 RDYDZ t 2.5 RDYD t 3.0 INTD t 2.5 DRQD t *1 MODH MB86291A www.DataSheet4U.com Unit Typ Max 100 MHz ns ns (External load of 20 pF) Value Unit Typ Max 11 ...
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... MB86291A Clock BCLKI Input setup and hold times BCLKI A2~A24, BS, CS, DTACK, DRACK Read/write enable (RD, WE) and input data (D) setup times BCLKI BS RD, WE D0~D31 16 1/f BCLKI t t HBCLKI LBCLKI ADS BSS CSS ADH DAKS DRKS DAKH RDS WES ...
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... DREQ output delay time BCLKI DREQ (output) INT output delay time BCLKI INT (output) RDY delay value (with respect to CS) BCLKI CS High-Z RDY (output) t RDYDZ MB86291A t DRQD t INTD High-Z t RDYDZ www.DataSheet4U.com 17 ...
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... MB86291A RDY/D output delay values BCLKI RD D0~D31 (output) RDY MODE signal hold time RESET MODE0~ MODE2 18 t RDD Output data t t RDYD RDYD t MODH www.DataSheet4U.com t RDDZ High-Z ...
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... WHSYNC1 SEO HEO 1) . The reference clock is DCLKI. Condi- Symbol tion Min t * 1.5 DEO t 1.5 DHSYNC t 1.5 DVSYNC t 1.5 DCSYNC t 1.5 DGV MB86291A www.DataSheet4U.com Value unit Typ Max 14.32 MHz MHz MHz Value unit Typ Max clock clock ns ns HSYNC 1 cycle ns ns Value unit ...
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... MB86291A Clock t CLK HSYNC signal setup and hold t HDCLKI DCLKI HSYNC (input) EO signal setup and hold VSYNC EO (input) Output signal delay DCLKO EO (output) HSYNC (output) VSYNC (output) CSYNC GV 20 1/f CLK t HCLK LCLK 1/f DCLKI t LDCLKI t t SHSYNC HHSYNC t t HEO ...
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... Video input CCLKI VI0~VI7 Condi- Symbol tion Min f CCLKI t 1 HCCLKI t 1 LCCLKI Condi- Symbol tion Min t 11 VIS t 2 VIH 1/f CLK t LCLK VIS VIH MB86291A www.DataSheet4U.com Value unit Typ Max 27 MHz ns ns Value unit Typ Max ...
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... MB86291A (4) PLL Standards Parameter Min Input frequency Output frequency Duty ratio 93.1 Jitter 150 22 Value Unit Typ Max 14.31818 MHz 200.45452 MHz Multiplied by 14 101.3 PLL output clock H/L pulse width ratio Cycle difference between two 180 ps consecutive cycles www.DataSheet4U.com Remarks ...
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... ORDERING INFORMATION Part Number MB86291APFVS Package 208-pin plastic QFP (FPT-208P-M04) MB86291A www.DataSheet4U.com Remarks 23 ...
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... MB86291A PACKAGE DIMENSION 208-pin plastic QFP (FPT-208P-M04) 30.60±0.20(1.205±.008)SQ 28.00±0.10(1.102±.004)SQ 156 157 INDEX 208 LEAD No. 1 0.50(.020) 2000 FUJITSU LIMITED F208020S-c-2 Note : Pins width and pins thickness include plating thickness. 105 104 53 "A" 52 0.22±0.05 ...
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... MB86291A FUJITSU LIMITED For further information please contact: Japan FUJITSU LIMITED Marketing Division Electronic Devices Shinjuku Dai-Ichi Seimei Bldg. 7-1, Nishishinjuku 2-chome, Shinjuku-ku, Tokyo 163-0721, Japan Tel: +81-3-5322-3353 Fax: +81-3-5322-3386 http://edevice.fujitsu.com/ North and South America FUJITSU MICROELECTRONICS AMERICA, INC. 3545 North First Street, San Jose, CA 95134-1804, U ...