X40420 XICOR [Xicor Inc.], X40420 Datasheet
X40420
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X40420 Summary of contents
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... See “Ordering Information” for more details For Custom Settings, call Xicor. DESCRIPTION The X40420/21 combines power-on reset control, watchdog timer, supply voltage supervision, and sec- ondary supervision, manual reset, and Block Lock protect serial EEPROM in one package. This combina- tion lowers system cost, reduces board space require- ments, and increases reliability ...
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... A battery switch circuit compares V and connects V to whichever is higher. This pro- OUT vides voltage to external SRAM or other circuits in the event of main power failure. The X40420/21 can drive 50mA from V to 250µA from V CC switches to V when V ...
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... RESET Output. (X40421) This open drain pin is an active LOW output which goes LOW whenever RESET V falls below V CC grammed time period (t and for t PURST RESET Output. (X40420) This pin is an active HIGH open drain output which goes HIGH when- ever V falls below V CC programmed time period (t and for t PURST 7 ...
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... X40420/X40421 – Preliminary PRINCIPLES OF OPERATION Power On Reset Applying power to the X40420/21 activates a Power On Reset Circuit that pulls the RESET/RESET pins active. This signal provides several benefits. – It prevents the system microprocessor from starting to operate with insufficient voltage. – It prevents the processor from operating prior to sta- bilization of the oscillator. – ...
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... However, in applications where the standard thresholds are not exactly right higher precision is needed in the threshold value, the X40420 trip points may be adjusted. The procedure is described below, and uses the applica- tion of a high voltage control signal. ...
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... See "Writing to the Control Registers" on page 8. The user must issue a stop, after sending this byte to the register, to initiate the nonvolatile cycle that stores WD1, WD0, PUP1, PUP0, and BP . The X40420 will not switches acknowledge any data bytes written after the first byte is OUT + 0 ...
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... X40420/X40421 – Preliminary Figure 6. V Set/Reset Sequence ( TRIPX New V applied = X Old V applied + | Error | X Error < MDE WEL: Write Enable Latch (Volatile) The WEL bit controls the access to the memory and to the Register during a write operation. This bit is a vola- tile latch that powers up in the LOW (disabled) state. ...
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... X40420/X40421 – Preliminary BP: Block Protect Bit (Nonvolatile) The Block Protect Bits BP determines which blocks of the array are write protected. A write to a protected block of memory is ignored. The block protect bit will prevent write operations to half the array segment. Protected Addresses (Size) 0 None 1 100h – ...
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... X40420/X40421 – Preliminary Figure 7. Valid Data Changes on the SDA Bus SCL SDA At power-up, the Fault Detection Register is defaulted to all “0”. The system needs to initialize this register to all “1” before the actual monitoring take place. In the event of any one of the monitored sources failed. The corresponding bits in the register will change from a “ ...
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... X40420/X40421 – Preliminary Figure 8. Valid Start and Stop Conditions SCL SDA Serial Acknowledge Acknowledge is a software convention used to indicate successful data transfer. The transmitting device, either master or slave, will release the bus after transmitting eight bits. During the ninth clock cycle, the receiver will pull the SDA line LOW to acknowledge that it received the eight bits of data ...
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... X40420/X40421 – Preliminary Figure 10. Byte Write Sequence Signals from the Master SDA Bus Signals from the Slave Page Write The device is capable of a page write operation initiated in the same manner as the byte write opera- tion; but instead of terminating the write cycle after the fi ...
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... X40420/X40421 – Preliminary Stops and Write Modes Stop conditions that terminate write operations must be sent by the master after sending at least 1 full data byte plus the subsequent ACK signal stop is issued in the middle of a data byte, or before 1 full data byte plus its associated ACK is sent, then the device will reset itself without performing the write ...
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... X40420/X40421 – Preliminary A similar operation called “Set Current Address” where the device will perform this operation if a stop is issued instead of the second start shown in Figure 15. The device will go into standby mode after the stop and all bus activity will be ignored until a start is detected. This operation loads the new address into the address counter ...
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... X40420/X40421 – Preliminary Figure 15. Random Address Read Sequence S t Signals from a the Master r t SDA Bus Signals from the Slave Figure 16. X40410/11 Addressing Slave Byte General Purpose Memory Control Register Fault Detection Register Word Address General Purpose Memory ...
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... X40420/X40421 – Preliminary ABSOLUTE MAXIMUM RATINGS Temperature under bias ................... –65°C to +135°C Storage temperature ........................ –65°C to +150°C Voltage on any pin with respect to V ......................................–1.0V to +7V SS D.C. output current ............................................... 5mA Lead temperature (soldering, 10 seconds)........ 300°C RECOMMENDED OPERATING CONDITIONS Temperature Min. ...
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... X40420/X40421 – Preliminary D.C. OPERATING CHARACTERISTICS (Continued) (Over the recommended operating conditions unless otherwise specified) Symbol Parameter (7) V Schmitt Trigger Input Hysteresis HYS • Fixed input level V • related level CC V Output LOW Voltage (SDA, RESET/ OL RESET, LOWLINE, V2FAIL, WDO) V Supply ...
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... X40420/X40421 – Preliminary CAPACITANCE Symbol (1) C Output Capacitance (SDA, RESET, RESET/LOWLINE, OUT V2FAIL, WDO) (1) C Input Capacitance (SCL, WP) IN Note: (1) This parameter is not 100% tested. EQUIVALENT A.C. OUTPUT LOAD CIRCUIT FOR OUT 4.6K 2.06K RESET SDA WDO/LOWLINE 30pF 30pF A.C. TEST CONDITIONS) ...
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... X40420/X40421 – Preliminary A.C. CHARACTERISTICS Symbol f SCL Clock Frequency SCL t Pulse width Suppression Time at inputs IN t SCL LOW to SDA Data Out Valid AA t Time the bus free before start of new transmission BUF t Clock LOW Time LOW t Clock HIGH Time HIGH t Start Condition Setup Time ...
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... X40420/X40421 – Preliminary WP Pin Timing START SCL SDA IN t SU:WP WP Write Cycle Timing SCL SDA th 8 Bit of Last Byte Nonvolatile Write Cycle Timing Symbol (1) t Write Cycle Time WC Note: ( the time from a valid stop condition at the end of a write sequence to the end of the self-timed internal nonvolatile write cycle. ...
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... X40420/X40421 – Preliminary RESET/RESET/MR Timings V TRIP1 PURST t R RESET V RVALID RESET MR LOW VOLTAGE AND WATCHDOG TIMINGS PARAMETERS (@25°C, VCC = 5V) Symbol ( RESET/RESET (Power down only) RPD1 TRIP1 LOWLINE RPDL TRIP1 (1) t LOWLINE to RESET/RESET delay (Power down only ...
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... X40420/X40421 – Preliminary Watchdog Time Out For 2-Wire Interface Start Clockin ( SCL SDA WDO Minimum Sequence to Reset WDT SCL SDA V Set/Reset Conditions TRIPX (V TRIPX t TSU WDO t VPS SCL 0 SDA A0h Start REV 1.2.14 7/12/02 Start t RSP < t WDO WDT Start Restart V /V2MON ...
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... X40420/X40421 – Preliminary Programming Specifications: V TRIP1 TRIP2 Parameter t WDO Program Voltage Setup time VPS t WDO Program Voltage Hold time VPH t V Level Setup time TSU TRIPX t V Level Hold (stable) time THD TRIPX t V Program Cycle WC TRIPX t Program Voltage Off time before next cycle ...
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... X40420/X40421 – Preliminary PACKAGING INFORMATION 14-Lead Plastic Small Outline Gullwing Package Type S Pin 1 Index Pin 1 0.014 (0.35) 0.020 (0.51) (4X) 7° 0.050 (1.27) 0.010 (0.25) 0.020 (0.50) 0° – 8° 0.016 (0.410) 0.037 (0.937) NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS) REV 1.2.14 7/12/02 0.150 (3.80) 0.158 (4.00) 0.336 (8.55) 0.345 (8.75) 0.004 (0.10) 0.010 (0.25) X 45° ...
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... X40420/X40421 – Preliminary PACKAGING INFORMATION 0° - 8° See Detail “A” NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS) REV 1.2.14 7/12/02 14-Lead Plastic, TSSOP, Package Type V .025 (.65) BSC .169 (4.3) .177 (4.5) .193 (4.9) .200 (5.1) .0075 (.19) .002 (.05) .0118 (.30) .006 (.15) .010 (.25) .019 (.50) .029 (.75) Detail A (20X) www.xicor.com .252 (6.4) BSC ...
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... X40420/X40421 – Preliminary ORDERING INFORMATION Monitored V TRIP1 V Supplies Range CC 2.9-5.5 4.6V±50mV 2.6-5.5 4.6V±50mV 1.6-3.6 2.9V±50mV PART MARK INFORMATION LIMITED WARRANTY Devices sold by Xicor, Inc. are covered by the warranty and patent indemnification provisions appearing in its Terms of Sale only. Xicor, Inc. makes no warranty, express, statutory, implied description regarding the information set forth herein or regarding the freedom of the described devices from patent infringement. ...