MAX3208EAUB+ Maxim Integrated Products, MAX3208EAUB+ Datasheet - Page 5

• Manufacturer Part Number: MAX3208EAUB+
• Description: IC ESD PROT DIFF 10-UMAX
• Manufacturer: Maxim Integrated Products
• Type: Diode Arraysr
• Series: MAX3208Er

Specifications of MAX3208EAUB+

• Power (watts): 444mW
• Polarization: 4 Channel Array - Unidirectional
• Mounting Type: Surface Mount
• Package / Case: 10-MSOP, Micro10™, 10-uMAX, 10-uSOP
• Capacitance Value: 10(Typ) pF
• Maximum Clamping Voltage: 105.5 V
• Number Of Elements Per Chip: 4
• Esd Protection Voltage: ±15@HBM|±15@Air Gap|±8@Contact Disc KV
• Maximum Leakage Current: 0.1 uA
• Channels: 4 Channels
• Clamping Voltage: 100 V
• Operating Voltage: - 0.3 V to + 6.0 V
• Termination Style: SMD/SMT
• Capacitance: 2 pF
• Maximum Operating Temperature: + 125 C
• Minimum Operating Temperature: - 40 C
• Dimensions: 3.05 (Max) mm W x 3.05 (Max) mm L
• Diode Type: ESD Protection
• Power Dissipation Pd: 444mW
• Diode Case Style: µMAX
• No. Of Pins: 10
• Termination Type: SMD
• Capacitance, Cd: 2.6pF
• Operating Temperature Range: -40°C To +125°C
• Rohs Compliant: Yes
• Filter Terminals: SMD
• Esd Threat Voltage Max: 15kV
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Voltage - Breakdown: -
• Voltage - Reverse Standoff (typ): -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Maximum protection against ESD damage results from
proper board layout (see the Layout Recommendations
section). A good layout reduces the parasitic series
inductance on the ground line, supply line, and protect-
ed signal lines. The MAX3205E/MAX3207E/MAX3208E
ESD diodes clamp the voltage on the protected lines
during an ESD event and shunt the current to GND or
V
defined as the forward voltage drop (V
tion diode, plus any supply voltage present on the cath-
ode.
For positive ESD pulses:
For negative ESD pulses:
The effect of the parasitic series inductance on the
lines must also be considered (Figure 1).
For positive ESD pulses:
For negative ESD pulses:
where I
Figure 1. Parasitic Series Inductance
CC
V
C
V
. In an ideal circuit, the clamping voltage (V
C
=
ESD
= −
V
CC
⎛
⎜
⎝
is the ESD current pulse.
V
F D
+
( )
Applications Information
PROTECTED
LINE
V
2
F D
( )
_______________________________________________________________________________________
+
1
V
⎛
⎜
⎝
C
L x
+
1
L1
V
= V
POSITIVE SUPPLY RAIL
⎛
⎜
⎝
C
L x
Design Considerations
1
= -V
CC
d I
(
ESD
dt
+ V
d I
F
L2
L3
GROUND RAIL
I/O_
(
D1
D2
ESD
dt
)
⎞
⎟ +
⎠
F
)
⎛
⎜
⎝
⎞
⎟ +
⎠
L
Dual, Quad, and Hex High-Speed
3
F
⎛
⎜
⎝
) of the protec-
L
x
Differential ESD-Protection ICs
2
d I
x
(
ESD
dt
d I
(
ESD
dt
)
⎞
⎟
⎠
⎞
⎟
⎠
C
)
) is
⎞
⎟
⎠
During an ESD event, the current pulse rises from zero
to peak value in nanoseconds (Figure 2). For example,
in a 15kV IEC 61000 Air-Gap Discharge ESD event, the
pulse current rises to approximately 45A in 1ns (di/dt =
45 x 10
tional 450V to the clamp voltage and represents
approximately 0.5in of board trace. Regardless of the
device’s specified diode clamp voltage, a poor layout
with parasitic inductance significantly increases the
effective clamp voltage at the protected signal line.
Minimize the effects of parasitic inductance by placing
the MAX3205E/MAX3207E/MAX3208E as close to the
connector (or ESD contact point) as possible.
A low-ESR 0.1µF capacitor is recommended between
V
tion possible. This bypass capacitor absorbs the
charge transferred by a positive ESD event. Ideally, the
supply rail (V
positive ESD strike without changing its regulated
value. All power supplies have an effective output
impedance on their positive rails. If a power supply’s
effective output impedance is 1Ω, then by using V = I x
R, the clamping voltage of V
tion V
event generates a current spike of 24A. The clamping
voltage increases by V
Again, a poor layout without proper bypassing increas-
es the clamping voltage. A ceramic chip capacitor
mounted as close as possible to the MAX3205E/
MAX3207E/MAX3208E V
this application. A bypass capacitor should also be
placed as close to the protected device as possible.
Figure 2. IEC 61000-4-2 ESD Generator Current Waveform
CC
t
R
and GND in order to get the maximum ESD protec-
= 0.7ns to 1ns
C
9
= I
). An inductance of only 10nH adds an addi-
100%
90%
10%
ESD
I
CC
) would absorb the charge caused by a
x R
OUT
30ns
. A +8kV IEC 61000-4-2 ESD
C
CC
= 24A x 1Ω, or V
60ns
pin is the best choice for
C
increases by the equa-
C
= 24V.
t
5