PIC16F677-I/P Microchip Technology, PIC16F677-I/P Datasheet - Page 188

• Manufacturer Part Number: PIC16F677-I/P
• Description: IC PIC MCU FLASH 2KX14 20DIP
• Manufacturer: Microchip Technology
• Series: PIC® 16Fr

Specifications of PIC16F677-I/P

• Program Memory Type: FLASH
• Program Memory Size: 3.5KB (2K x 14)
• Package / Case: 20-DIP (0.300", 7.62mm)
• Mfg Application Notes: Intro to Capacitive Sensing Appl Notes Layout and Physical Design Appl Note
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: I²C, SPI
• Peripherals: Brown-out Detect/Reset, POR, WDT
• Number Of I /o: 18
• Eeprom Size: 256 x 8
• Ram Size: 128 x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC16F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 128 B
• Interface Type: SSP
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 17
• Number Of Timers: 2
• Operating Supply Voltage: 2 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: Through Hole
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, DM163014, DM164120-4
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12-ch x 10-bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC162061 - HEADER INTRFC MPLAB ICD2 20PINACICE0203 - MPLABICE 20P 300 MIL ADAPTER
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

PIC16F631/677/685/687/689/690
13.12.2
When the R/W bit of the address byte is clear and an
address match occurs, the R/W bit of the SSPSTAT
register is cleared. The received address is loaded into
the SSPBUF register.
When the address byte overflow condition exists, then
no Acknowledge (ACK) pulse is given. An overflow
condition is defined as either bit BF of the SSPSTAT
register is set, or bit SSPOV of the SSPCON register is
set. This is an error condition due to the user’s firm-
ware.
An SSP interrupt is generated for each data transfer
byte. Flag bit SSPIF of the PIR1 register must be
cleared in software. The SSPSTAT register is used to
determine the status of the byte.
FIGURE 13-8:
DS41262C-page 186
SDA
SCL
SSPIF (PIR1<3>)
BF (SSPSTAT<0>)
SSPOV (SSPCON<6>)
S
RECEPTION
A7 A6 A5 A4 A3 A2 A1
1
2
Receiving Address
3
4
I
2
C™ WAVEFORMS FOR RECEPTION (7-BIT ADDRESS)
5
6
7
R/W = 0
8
ACK
9
D7
1
D6
2
SSPBUF register is read
Preliminary
Receiving Data
D5
3
Cleared in software
D4
Bit SSPOV is set because the SSPBUF register is still full.
4
D3
5
D2
6
D1
7
D0
8
ACK
9
D7
1
D6
2
D5
Receiving Data
3
D4
4
© 2006 Microchip Technology Inc.
ACK is not sent.
D3
5
D2
6
D1
7
D0
8
ACK
9
transfer
Bus Master
terminates
P