PIC12F635-I/P Microchip Technology, PIC12F635-I/P Datasheet
PIC12F635-I/P
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PIC12F635-I/P Summary of contents
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... PIC12F635/PIC16F636/639 *8-bit, 8-pin Devices Protected by Microchip’s Low Pin Count Patent Patent No. 5,847,450. Additional U.S. and foreign patents and applications may be issued or pending. © 2005 Microchip Technology Inc. 8/14-Pin Flash-Based, 8-Bit CMOS Microcontrollers with nanoWatt Technology Preliminary Data Sheet DS41232B ...
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... PowerCal, PowerInfo, PowerMate, PowerTool, rfLAB, rfPICDEM, Select Mode, Smart Serial, SmartTel and Total Endurance are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. ...
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... PIC12F635/PIC16F636/639 8/14-Pin Flash-Based, 8-Bit CMOS Microcontrollers With nanoWatt Technology High-Performance RISC CPU: • Only 35 instructions to learn: - All single-cycle instructions except branches • Operating speed – 20 MHz oscillator/clock input - DC – 200 ns instruction cycle • Interrupt capability • 8-level deep hardware stack • Direct, Indirect and Relative Addressing modes Special Microcontroller Features: • ...
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... PIC12F635/PIC16F636/639 Program Memory Device Flash (words) SRAM (bytes) PIC12F635 1024 PIC16F636 2048 PIC16F639 2048 Pin Diagrams 8-Pin PDIP, SOIC, DFN-S GP5/T1CKI/OSC1/CLKIN GP4/T1G/OSC2/CLKOUT GP3/MCLR/V 14-Pin PDIP, SOIC, TSSOP RA5/T1CKI/OSC1/CLKIN RA4/T1G/OSC2/CLKOUT RA3/MCLR/V RC4/C2OUT 20-Pin SSOP RA5/T1CKI/OSC1/CLKIN RA4/T1G/OSC2/CLKOUT RA3/MCLR/V RC4/C2OUT RC3/LFDATA/RSSI/CCLK/SDIO Note 1: Any references to PORTA, RAn, TRISA and TRISAn refer to GPIO, GPn, TRISIO and TRISIOn, respectively. ...
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... When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are using. Customer Notification System Register on our web site at www.microchip.com to receive the most current information on all of our products. © 2005 Microchip Technology Inc. PIC12F635/PIC16F636/639 Preliminary 185 DS41232B-page 3 ...
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... PIC12F635/PIC16F636/639 NOTES: DS41232B-page 4 Preliminary © 2005 Microchip Technology Inc. ...
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... T0CKI Cryptographic Module Comparator and Reference C1IN- C1IN+ C1OUT © 2005 Microchip Technology Inc. PIC12F635/PIC16F636/639 The PIC12F635/PIC16F636/639 devices are covered by this data sheet. Figure 1-1 shows a block diagram of the PIC12F635/PIC16F636/639 devices. Table 1-1 shows the pinout description. ® Mid-Range Sales 8 Data Bus ...
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... PIC12F635/PIC16F636/639 FIGURE 1-2: PIC16F636 BLOCK DIAGRAM Configuration 13 Program Counter Flash Program 8-level Stack Memory Program 14 Bus Instruction reg Direct Addr 8 Power-up Oscillator Instruction Start-up Timer Decode and Power-on Control Watchdog OSC1/CLKIN Timing Brown-out Generation OSC2/CLKOUT Programmable Low-Voltage Detect 8 MHz 31 kHz Wake-up ...
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... Low-voltage Detect 8 MHz 31 kHz Internal Internal Oscillator Oscillator MCLR V Timer0 T0CKI K Module EELOQ and Reference C1IN- C1IN+ C1OUT C2IN- C2IN+ C2OUT © 2005 Microchip Technology Inc. PIC12F635/PIC16F636/639 8 Data Bus RAM 128 bytes (13-bit) File Registers (1) RAM Addr 9 Addr MUX Indirect 7 8 Addr ...
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... PIC12F635/PIC16F636/639 TABLE 1-1: PIC12F635 PINOUT DESCRIPTIONS Name Function GP5/T1CKI/OSC1/CLKIN GP5 T1CKI OSC1 CLKIN GP4/T1G/OSC2/CLKOUT GP4 T1G OSC2 CLKOUT GP3/MCLR/V GP3 PP MCLR V PP GP2/T0CKI/INT/C1OUT GP2 T0CKI INT C1OUT GP1/C1IN-/ICSPCLK GP1 C1IN- ICSPCLK GP0/C1IN+/ICSPDAT/ULPWU GP0 C1IN+ ICSPDAT ULPWU Legend Analog input or output ...
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... RA0 C1IN+ ICSPDAT ULPWU Legend Analog input or output HV = High Voltage TTL = TTL compatible input © 2005 Microchip Technology Inc. PIC12F635/PIC16F636/639 Input Output Type Type D — Power supply for microcontroller. TTL CMOS General purpose I/O. Individually controlled interrupt-on-change. Individually enabled pull-up/pull-down. ST — ...
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... PIC12F635/PIC16F636/639 TABLE 1-3: PIC16F639 PINOUT DESCRIPTIONS Name Function RA5/T1CKI/OSC1/CLKIN RA5 T1CKI OSC1 CLKIN RA4 RA4/T1G/OSC2/CLKOUT T1G OSC2 CLKOUT RA3 RA3/MCLR/V PP MCLR V PP RC5 RC5 RC4/C2OUT RC4 C2OUT RC3/LFDATA/RSSI/CCLK/SDIO RC3 LFDATA RSSI CCLK SDIO V V DDT DDT LCZ LCZ LCY LCY LCX ...
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... Program Memory Organization The PIC12F635/PIC16F636/639 devices have a 13-bit program counter capable of addressing program memory space. Only the first (0000h-03FFh, for the PIC12F635) and (0000h-07FFh, for the PIC16F636/639) is physically implemented. Accessing a location above these boundaries will cause a wrap around within the first space ...
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... PIC12F635/PIC16F636/639 2.2.1 GENERAL PURPOSE REGISTER The register file is organized for the PIC12F635 and 128 x 8 for the PIC16F636/639. Each register is accessed, either directly or indirectly, through the File Select Register, FSR (see Section 2.4 “Indirect Addressing, INDF and FSR Registers”). 2.2.2 ...
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... FIGURE 2-3: PIC12F635 SPECIAL FUNCTION REGISTERS File Address (1) Indirect addr. 00h Indirect addr. TMR0 01h OPTION_REG 81h PCL 02h PCL STATUS 03h STATUS FSR 04h FSR GPIO 05h TRISIO 06h 07h 08h 09h PCLATH 0Ah PCLATH INTCON 0Bh INTCON PIR1 0Ch ...
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... PIC12F635/PIC16F636/639 FIGURE 2-4: PIC16F636/639 SPECIAL FUNCTION REGISTERS File Address (1) Indirect addr. 00h Indirect addr. TMR0 01h OPTION_REG 81h PCL 02h PCL STATUS 03h STATUS FSR 04h FSR PORTA 05h TRISA 06h PORTC 07h TRISC 08h 09h PCLATH 0Ah PCLATH INTCON 0Bh ...
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... TABLE 2-2: PIC12F635 SPECIAL FUNCTION REGISTERS SUMMARY BANK 0 Addr Name Bit 7 Bit 6 Bit 5 Bank 0 00h INDF Addressing this location uses contents of FSR to address data memory (not a physical register) 01h TMR0 Timer0 Module Register 02h PCL Program Counter’s (PC) Least Significant Byte ...
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... PIC12F635/PIC16F636/639 TABLE 2-3: PIC12F635 SPECIAL FUNCTION REGISTERS SUMMARY BANK 1 Addr Name Bit 7 Bit 6 Bank 1 80h INDF Addressing this location uses contents of FSR to address data memory (not a physical register) 81h OPTION_REG RAPU INTEDG 82h PCL Program Counter’s (PC) Least Significant Byte 83h ...
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... Other (non Power-up) Resets include MCLR Reset and Watchdog Timer Reset during normal operation. 2: MCLR and WDT Reset do not affect the previous value data latch. The RAIF bit will be cleared upon Reset but will set again if the mismatch exists. © 2005 Microchip Technology Inc. PIC12F635/PIC16F636/639 Bit 4 Bit 3 Bit 2 TO ...
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... PIC12F635/PIC16F636/639 TABLE 2-5: PIC16F636/639 SPECIAL FUNCTION REGISTERS SUMMARY BANK 1 Addr Name Bit 7 Bit 6 Bank 1 80h INDF Addressing this location uses contents of FSR to address data memory (not a physical register) 81h OPTION_REG RAPU INTEDG 82h PCL Program Counter’s (PC) Least Significant Byte 83h ...
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... TABLE 2-6: PIC12F635/PIC16F636/639 SPECIAL FUNCTION REGISTERS SUMMARY BANK 2 Addr Name Bit 7 Bit 6 Bank 2 10Ch — Unimplemented 10Dh — Unimplemented 10Eh — Unimplemented 10Fh — Unimplemented 110h CRCON GO/DONE ENC/DEC (2) 111h CRDAT0 Cryptographic Data Register 0 (2) 112h CRDAT1 Cryptographic Data Register 1 (2) ...
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... PIC12F635/PIC16F636/639 2.2.2.1 Status Register The Status register, shown in Register 2-1, contains: • the arithmetic status of the ALU • the Reset status • the bank select bits for data memory (SRAM) The Status register can be the destination for any instruction, like any other register. If the Status register is the destination for an instruction that affects the bits, then the write to these three bits is disabled ...
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... Legend Readable bit - n = Value at POR © 2005 Microchip Technology Inc. PIC12F635/PIC16F636/639 Note: To achieve a 1:1 prescaler assignment for TMR0, assign the prescaler to the WDT by setting the (OPTION_REG<3>). “Prescaler”. R/W-1 R/W-1 R/W-1 R/W-1 T0CS T0SE ...
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... PIC12F635/PIC16F636/639 2.2.2.3 INTCON Register The INTCON register is a readable and writable register which contains the various enable and flag bits for TMR0 register overflow, PORTA change and external RA2/INT pin interrupts. REGISTER 2-3: INTCON – INTERRUPT CONTROL REGISTER (ADDRESS: 0Bh OR 8Bh) ...
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... TMR1IE: Timer1 Interrupt Enable bit 1 = Enables the Timer1 interrupt 0 = Disables the Timer1 interrupt Note 1: PIC16F636/639 only. Legend Readable bit - n = Value at POR © 2005 Microchip Technology Inc. PIC12F635/PIC16F636/639 Note: Bit PEIE (INTCON<6>) must be set to enable any peripheral interrupt. R/W-0 R/W-0 R/W-0 R/W-0 ...
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... PIC12F635/PIC16F636/639 2.2.2.5 PIR1 Register The PIR1 register contains the interrupt flag bits, as shown in Register 2-5. REGISTER 2-5: PIR1 – PERIPHERAL INTERRUPT REQUEST REGISTER 1 (ADDRESS: 0Ch) R/W-0 R/W-0 EEIF LVDIF bit 7 bit 7 EEIF: EEPROM Write Operation Interrupt Flag bit 1 = The write operation completed (must be cleared in software) ...
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... Note 1: BODEN<1:0> the Configuration Word register for SBODEN to control the Brown-out Detect module. Legend Readable bit - n = Value at POR © 2005 Microchip Technology Inc. PIC12F635/PIC16F636/639 The PCON register also controls the Ultra Low-Power Wake-up and software enable of the BOD. The PCON register bits are shown in Register 2-6. R/W-0 R/W-1 ...
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... Refer to the Application Note AN556, “Implementing a Table Read” (DS00556). 2.3.2 STACK The PIC12F635/PIC16F636/639 family has an 8- level x 13-bit wide hardware stack (see Figure 2-1). The stack space is not part of either program or data space and the Stack Pointer is not readable or writable. ...
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... Writing to the INDF register indirectly results operation (although Status bits may be affected). An effective 9-bit address is obtained by concatenating the 8-bit FSR and the IRP bit (STATUS<7>), as shown in Figure 2-6. FIGURE 2-6: DIRECT/INDIRECT ADDRESSING PIC12F635/PIC16F636/639 Direct Addressing From Opcode 6 RP1 RP0 Bank Select ...
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... PIC12F635/PIC16F636/639 NOTES: DS41232B-page 28 Preliminary © 2005 Microchip Technology Inc. ...
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... CLOCK SOURCES 3.1 Overview The PIC12F635/PIC16F636/639 has a wide variety of clock sources and selection features to allow used in a wide range of applications, while maximizing performance and minimizing power consumption. Figure 3-1 illustrates a block diagram PIC12F635/PIC16F636/639 clock sources. Clock sources can be configured from external oscillators, quartz crystal resonators, ceramic resonators and Resistor-Capacitor (RC) circuits ...
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... The OST ensures that the oscillator circuit, using a quartz crystal resonator or ceramic resonator, has started and is providing a stable system clock to the PIC12F635/ PIC16F636/639. When switching between clock sources, a delay is required to allow the new clock to stabilize. Table 3-1 shows oscillator delay examples ...
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... The Oscillator Start-up Timer (OST) is disabled when EC mode is selected. Therefore, there is no delay in operation after a Power-on Reset (POR) or wake-up from Sleep. Because the PIC12F635/PIC16F636/639 design is fully static, stopping the external clock input will have the effect of halting the device while leaving all data intact ...
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... The user also needs to take into account EXT variation due to tolerance of external RC components used. DS41232B-page 32 3.4 Internal Clock Modes The PIC12F635/PIC16F636/639 has two independent, internal oscillators that can be configured or selected as the system clock source. 1. The HFINTOSC Oscillator) is factory calibrated and operates at 8 MHz. The frequency of the HFINTOSC can be user adjusted ± ...
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... Minimum frequency Legend Readable bit - n = Value at POR © 2005 Microchip Technology Inc. PIC12F635/PIC16F636/639 When the OSCTUNE register is modified, the HFINTOSC frequency will begin shifting to the new frequency. The HFINTOSC clock will stabilize within 1 ms. Code execution continues during this shift. There is no indication that the shift has occurred ...
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... PIC12F635/PIC16F636/639 3.4.3 LFINTOSC The Low-Frequency Internal Oscillator (LFINTOSC uncalibrated (approximate) 31 kHz internal clock source. The output of the LFINTOSC connects to a postscaler and multiplexer (see Figure 3-1). 31 kHz can be selected via software using the IRCF bits (see Section 3.4.4 “Frequency Select Bits (IRCF)”). The ...
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... System clock is switched to external clock source. 3.6.3 CHECKING EXTERNAL/INTERNAL CLOCK STATUS Checking the state of the OSTS bit (OSCCON<3>) will confirm if the PIC12F635/PIC16F636/639 is running from the external clock source, as defined by the FOSC bits in the Configuration Word register (Register 12-1) or the internal oscillator. Preliminary DS41232B-page 35 ...
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... PIC12F635/PIC16F636/639 FIGURE 3-7: TWO-SPEED START- INTOSC T T OST OSC1 0 1 OSC2 Program Counter System Clock 3.7 Fail-Safe Clock Monitor The Fail-Safe Clock Monitor (FSCM) is designed to allow the device to continue to operate in the event of an oscillator failure. The FSCM can detect oscillator failure at any point after the device has exited a Reset or Sleep condition and the Oscillator Start-up Timer (OST) has expired ...
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... FAIL-SAFE CONDITION CLEARING The Fail-Safe condition is cleared after a Reset, the execution of a SLEEP instruction modification of the SCS bit. While in Fail-Safe condition, the PIC12F635/ PIC16F636/639 uses the internal oscillator as the system clock source. The IRCF bits (OSCCON<6:4>) can be modified to adjust the internal oscillator frequency without exiting the Fail-Safe condition ...
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... PIC12F635/PIC16F636/639 REGISTER 3-2: OSCCON – OSCILLATOR CONTROL REGISTER (ADDRESS: 8Fh) U-0 R/W-1 — IRCF2 bit 7 bit 7 Unimplemented: Read as ‘0’ bit 6-4 IRCF<2:0>: Nominal Internal Oscillator Frequency Select bits 000 = 31 kHz 001 = 125 kHz 010 = 250 kHz 011 = 500 kHz 100 = 1 MHz ...
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... BCF STATUS,RP1 ; © 2005 Microchip Technology Inc. PIC12F635/PIC16F636/639 4.2 Additional Pin Functions Every PORTA pin on the PIC12F635/PIC16F636/639 has an interrupt-on-change option and a weak pull-up/ pull-down option. RA0 has an Ultra Low-Power Wake- up option. The next three sections describe these functions. 4.2.1 WEAK PULL-UP/PULL-DOWN Each of the PORTA pins, except RA3, has an internal weak pull-up and pull-down ...
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... PIC12F635/PIC16F636/639 REGISTER 4-1: WDA – WEAK PULL-UP/PULL-DOWN REGISTER (ADDRESS: 97h) U-0 — bit 7 bit 7-6 Unimplemented: Read as ‘0’ bit 5-4 WDA<5:4>: Pull-up/Pull-down Selection bits 1 = Pull-up selected 0 = Pull-down selected bit 3 Unimplemented: Read as ‘0’ bit 2-0 WDA<2:0>: Pull-up/Pull-down Selection bits 1 = Pull-up selected ...
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... PORTA pin configured as an input (tri-stated PORTA pin configured as an output Note 1: TRISA<3> always reads ‘1’. 2: TRISA<5:4> always reads ‘1’ in XT, HS and LP Oscillator modes. Legend Readable bit - n = Value at POR © 2005 Microchip Technology Inc. PIC12F635/PIC16F636/639 U-0 R/W-x R/W-x R-x — RA5 RA4 ...
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... PIC12F635/PIC16F636/639 4.2.2 INTERRUPT-ON-CHANGE Each of the PORTA pins is individually configurable as an interrupt-on-change pin. Control bits, IOCAx, enable or disable the interrupt function for each pin. Refer to Register 4-5. The interrupt-on-change is disabled on a Power-on Reset. For enabled interrupt-on-change pins, the values are compared with the old value latched on the last read of PORTA. The ‘ ...
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... Programmable Low-Voltage Detect or temperature sensor. Note: For more information, refer to the Application Note AN879, “Using the Microchip Ultra Low-Power Wake-up Module” (DS00879). © 2005 Microchip Technology Inc. PIC12F635/PIC16F636/639 EXAMPLE 4-2: ULTRA LOW-POWER WAKE-UP INITIALIZATION BCF STATUS,RP0 BCF STATUS,RP1 ...
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... PIC12F635/PIC16F636/639 4.2.4 PIN DESCRIPTIONS AND DIAGRAMS Each PORTA pin is multiplexed with other functions. The pins and their combined functions are briefly described here. For specific information about individual functions, such as the comparator, refer to the appropriate section in this data sheet. FIGURE 4-1: ...
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... RD PORTA To Comparator Note 1: Comparator mode determines Analog Input mode. © 2005 Microchip Technology Inc. PIC12F635/PIC16F636/639 4.2.4.3 Figure 4-3 shows the diagram for this pin. The RA2 pin is configurable to function as one of the following: • a general purpose I/O • the clock input for TMR0 • ...
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... PIC12F635/PIC16F636/639 4.2.4.4 RA3/MCLR/V PP Figure 4-4 shows the diagram for this pin. The RA3 pin is configurable to function as one of the following: • a general purpose input • as Master Clear Reset with weak pull-up • a high-voltage detect for Program mode entry FIGURE 4-4: BLOCK DIAGRAM OF RA3 ...
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... Oscillator modes are XT, HS, LP, LPTMR1 and CLKOUT Enable. 2: With CLKOUT option. © 2005 Microchip Technology Inc. PIC12F635/PIC16F636/639 4.2.4.6 Figure 4-6 shows the diagram for this pin. The RA5 pin is configurable to function as one of the following: • a general purpose I/O • a TMR1 clock input • ...
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... PIC12F635/PIC16F636/639 TABLE 4-1: SUMMARY OF REGISTERS ASSOCIATED WITH PORTA Add Name Bit 7 Bit 6 r 05h PORTA — — 0Bh/ INTCON GIE PEIE 8Bh 0Eh TMR1L Holding Register for the Least Significant Byte of the 16-bit TMR1 Register 0Fh TMR1H Holding Register for the Most Significant Byte of the 16-bit TMR1 Register ...
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... I/O • an analog input to the comparator 4.3.2 RC1/C2IN- The RC1 pin is configurable to function as one of the following: • a general purpose I/O • an analog input to the comparator © 2005 Microchip Technology Inc. PIC12F635/PIC16F636/639 FIGURE 4-7: BLOCK DIAGRAM OF RC0 AND RC1 Data Bus ...
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... PIC12F635/PIC16F636/639 4.3.6 RC4/C2OUT The RC4 pin is configurable to function as one of the following: • a general purpose I/O • a digital output from the comparator FIGURE 4-9: BLOCK DIAGRAM OF RC4 C2OUT Enable C2OUT Data Bus PORTC TRISC RD TRISC RD PORTC DS41232B-page I/O pin V SS Preliminary © 2005 Microchip Technology Inc. ...
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... CMCON0 C2OUT C1OUT 87h TRISC — — Legend unknown unchanged, — = unimplemented locations read as ‘0’. Shaded cells are not used by PORTC. © 2005 Microchip Technology Inc. PIC12F635/PIC16F636/639 U-0 R/W-x R/W-x R/W-x — RC5 RC4 RC3 Writable bit U = Unimplemented bit, read as ‘0’ ...
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... PIC12F635/PIC16F636/639 NOTES: DS41232B-page 52 Preliminary © 2005 Microchip Technology Inc. ...
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... Timer Note 1: T0SE, T0CS, PSA, PS<2:0> are bits in the Option register, WDTPS<3:0> are bits in the WDTCON register. © 2005 Microchip Technology Inc. PIC12F635/PIC16F636/639 Counter mode is selected by setting the T0CS bit (OPTION_REG<5>). In this mode, the Timer0 module will increment either on every rising or falling edge of pin RA2/T0CKI ...
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... Note 1: A dedicated 16-bit WDT postscaler is available for the PIC12F635/PIC16F636/639. See Section 12.11 “Watchdog Timer (WDT)” for more information. Legend Readable bit - n = Value at POR DS41232B-page 54 (and a OSC (and OSC R/W-1 R/W-1 R/W-1 ...
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... OPTION_REG RAPU INTEDG 85h TRISA — — Legend: — = Unimplemented locations, read as ‘0’ unchanged unknown. Shaded cells are not used by the Timer0 module. © 2005 Microchip Technology Inc. PIC12F635/PIC16F636/639 EXAMPLE 5-1: BCF STATUS,RP0 BCF STATUS,RP1 CLRWDT CLRF TMR0 BSF STATUS,RP0 ...
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... PIC12F635/PIC16F636/639 NOTES: DS41232B-page 56 Preliminary © 2005 Microchip Technology Inc. ...
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... OSC2/T1G INTOSC No CLKOUT T1OSCEN Note 1: Timer1 increments on the rising edge. 2: C2OUT for PIC16F636/639, C1OUT for PIC12F635 Buffer is low-power type when using LP oscillator, or high-speed type when using T1CKI. © 2005 Microchip Technology Inc. PIC12F635/PIC16F636/639 The Timer1 Control register (T1CON), shown in Register 6-1, is used to enable/disable Timer1 and select the various features of the Timer1 module ...
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... PIC12F635/PIC16F636/639 6.1 Timer1 Modes of Operation Timer1 can operate in one of three modes: • 16-bit timer with prescaler • 16-bit synchronous counter • 16-bit asynchronous counter In Timer mode, Timer1 is incremented on every instruction cycle. In Counter mode, Timer1 is incremented on the rising edge of the external clock input T1CKI. In addition, the Counter mode clock can be synchronized to the microcontroller system clock or run asynchronously ...
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... Note 1: T1GINV bit inverts the Timer1 gate logic, regardless of source. 2: TMR1GE bit must be set to use either T1G pin or C2OUT, as selected by the T1GSS bit (CMCON1<1>), as a Timer1 gate source. Legend Readable bit - n = Value at POR © 2005 Microchip Technology Inc. PIC12F635/PIC16F636/639 R/W-0 R/W-0 R/W-0 (1) (2) /4) ...
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... PIC12F635/PIC16F636/639 6.5 Timer1 Operation in Asynchronous Counter Mode If control bit T1SYNC (T1CON<2>) is set, the external clock input is not synchronized. The timer continues to increment asynchronous to the internal phase clocks. The timer will continue to run during Sleep and can generate an interrupt on overflow, which will wake-up the processor ...
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... RA1 IN bit 2-0 CM<2:0>: Comparator Mode bits Figure 7-4 shows the Comparator modes and CM<2:0> bit settings. Note 1: PIC16F636/639 only. Reads as ‘0’ for PIC12F635. 2: PIC12F635 bit names are COUT and CINV. Legend Readable bit - n = Value at POR © 2005 Microchip Technology Inc. ...
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... PIC12F635/PIC16F636/639 7.1 Comparator Operation A single comparator is shown in Figure 7-1 along with the relationship between the analog input levels and the digital output. When the analog input at V than the analog input V -, the output of the comparator digital low level. When the analog input at V ...
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... Section 15.0 “Electrical Specifications”. Note: Comparator interrupts should be disabled during a Comparator mode change. Otherwise, a false interrupt may occur. FIGURE 7-3: COMPARATOR I/O OPERATING MODES FOR PIC12F635 Comparator Reset (POR Default Value – Low Power) CM<2:0> = 000 GP1/CIN- A GP0/CIN+ A ...
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... PIC12F635/PIC16F636/639 FIGURE 7-4: COMPARATOR I/O OPERATING MODES FOR PIC16F636/639 Comparator Reset (POR Default Value) CM<2:0> = 000 RA1 Off RA0 RC1 C2 Off RC0 Two Independent Comparators CM<2:0> = 100 RA1 C1OUT RA0 RC1 C2OUT RC0 Two Common Reference Comparators CM<2:0> = 011 RA1 C1OUT ...
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... FIGURE 7-5: PIC12F635 COMPARATOR C1 OUTPUT BLOCK DIAGRAM To TMR1 To C1OUT pin To Data Bus RD CMCON Set C2IF bit Note 1: Comparator 1 output is latched on falling edge of T1 clock source. FIGURE 7-6: PIC16F636/639 COMPARATOR C1 OUTPUT BLOCK DIAGRAM To C1OUT pin To Data Bus Set C1IF bit © 2005 Microchip Technology Inc. ...
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... Timer1 gate source is T1G pin (RA4 must be configured as digital input Timer1 gate source is Comparator 2 output bit 0 C2SYNC: Comparator 2 Synchronize bit output synchronized with falling edge of Timer1 clock output not synchronized with Timer1 clock Note 1: C2SYNC is C1SYNC in PIC12F635. Legend Readable bit - n = Value at POR DS41232B-page 66 C2SYNC ...
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... Timer1 clock source and Timer1 increments on the rising edge of its clock source. See Figure 7-6, Comparator C2 Output Block Diagram and Figure 5-1, Timer1 on the PIC12F635/ PIC16F636/639 Block Diagram for more information recommended to synchronize Comparator 2 with Timer1 by setting the C2SYNC bit when Comparator 2 is used as the Timer1 gate source ...
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... PIC12F635/PIC16F636/639 7.6 Comparator Reference The comparator module also allows the selection of an internally generated voltage reference for one of the comparator inputs. The VRCON register (Register 7-3) controls the voltage reference module shown in Figure 7-8. 7.6.1 CONFIGURING THE VOLTAGE REFERENCE The voltage reference can output 32 distinct voltage levels high range and low range ...
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... DD Legend Readable bit - n = Value at POR © 2005 Microchip Technology Inc. PIC12F635/PIC16F636/639 While the comparator is enabled during Sleep, an interrupt will wake-up the device. If the GIE bit (INTCON<7>) is set, the device will jump to the interrupt vector (0004h) and if clear, continues execution with the next instruction. If the device wakes up from Sleep, the contents of the CMCON0, CMCON1 and VRCON registers are not affected ...
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... PIC12F635/PIC16F636/639 NOTES: DS41232B-page 70 Preliminary © 2005 Microchip Technology Inc. ...
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... Shaded cells are not used by the comparator or comparator voltage reference module. Note 1: PIC16F636/639 only. © 2005 Microchip Technology Inc. PIC12F635/PIC16F636/639 8.1 Voltage Trip Points The PIC12F635/PIC16F636/639 device supports eight internal PLVD trip points. See Register 8-1 for available PLVD trip point voltages. U-0 R-0 R/W-0 U-0 — ...
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... PIC12F635/PIC16F636/639 NOTES: DS41232B-page 72 Preliminary © 2005 Microchip Technology Inc. ...
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... EEADR7 EEADR6 bit 7 bit 7-0 EEADR: Specifies 1 of 256 Locations for EEPROM Read/Write Operation bits Note 1: PIC16F636/639 only. Read as ‘0’ on PIC12F635. Legend Readable bit - n = Value at POR © 2005 Microchip Technology Inc. PIC12F635/PIC16F636/639 The EEPROM data memory allows byte read and write. ...
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... PIC12F635/PIC16F636/639 9.1 EECON1 AND EECON2 Registers EECON1 is the control register with four low-order bits physically implemented. The upper four bits are non- implemented and read as ‘0’s. Control bits RD and WR initiate read and write, respectively. These bits cannot be cleared, only set in software ...
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... EEPROM. The WREN bit is not cleared by hardware. © 2005 Microchip Technology Inc. PIC12F635/PIC16F636/639 After a write sequence has been initiated, clearing the WREN bit will not affect this write cycle. The WR bit will be inhibited from being set unless the WREN bit is set. ...
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... PIC12F635/PIC16F636/639 9.5 Protection Against Spurious Write There are conditions when the user may not want to write to the data EEPROM memory. To protect against spurious EEPROM writes, various mechanisms have been built in. On power-up, WREN is cleared. Also, the Power-up Timer (nominal 64 ms duration) prevents EEPROM write ...
Page 79
... L Encoder License EE OQ Agreement”. ® The “K L Encoder License Agreement” may accessed through the Microchip web site located at www.microchip.com Further information may obtained by contacting your local Microchip Sales Representative. © 2005 Microchip Technology Inc. PIC12F635/PIC16F636/639 Preliminary DS41232B-page 77 ...
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... PIC12F635/PIC16F636/639 NOTES: DS41232B-page 78 Preliminary © 2005 Microchip Technology Inc. ...
Page 81
... The signal levels from all 3 channels are combined such that the limiter attenuates all 3 channels uniformly, in respect to the channel with the strongest signal. © 2005 Microchip Technology Inc. PIC12F635/PIC16F636/639 11.2 Modulation Circuit The modulation circuit consists of a modulation transistor (FET), internal tuning capacitors and external LC antenna components ...
Page 82
... PIC12F635/PIC16F636/639 11.6 AGC Control The AGC controls the variable attenuator to limit the internal signal voltage to avoid saturation of internal amplifiers and demodulators (Refer to Section 11.4 “Variable Attenuator”). The signal levels from all 3 channels are combined such that AGC attenuates all 3 channels uniformly in respect to the channel with the strongest signal ...
Page 83
... If the noise source is ignored, the AFE can return to a lower standby current draw state. © 2005 Microchip Technology Inc. PIC12F635/PIC16F636/639 The timer is reset when the: • CS pin is low (any SPI command). • Output enable filter is disabled. ...
Page 84
... PIC12F635/PIC16F636/639 FIGURE 11-1: FUNCTIONAL BLOCK DIAGRAM – ANALOG FRONT-END LCX Tune X RF Mod Lim LCCOM LCY Tune Y RF Mod Lim LCCOM LCZ Tune Z RF Mod Lim LCCOM AGC Preserve To Modulation Transistors DS41232B-page 82 AGC Detector Sensitivity Control X A AGC Detector Sensitivity Control Y ...
Page 85
... FIGURE 11-2: LC INPUT PATH © 2005 Microchip Technology Inc. PIC12F635/PIC16F636/639 Preliminary DS41232B-page 83 ...
Page 86
... PIC12F635/PIC16F636/639 FIGURE 11-3: BIDIRECTIONAL PASSIVE KEYLESS ENTRY (PKE) SYSTEM APPLICATION EXAMPLE LED UHF Receiver LF Transmitter/ Receiver Base Station FIGURE 11-4: PASSIVE KEYLESS ENTRY (PKE) TRANSPONDER CONFIGURATION EXAMPLE +3V 315 MHz RF Circuitry (UHF TX) LFDATA/RSSI/CCLK/SDIO +3V air-core coil DS41232B-page 84 Ant. X Ant. Y Ant Data LED 5 16 ...
Page 87
... Missing cycles may result in failing the output enable condition. FIGURE 11-5: OUTPUT ENABLE FILTER TIMING T STAB ( AGC PAGC Demodulator Output AFE Wake-up and AGC Stabilization © 2005 Microchip Technology Inc. PIC12F635/PIC16F636/639 ) and OEH . OEH Required Output Enable Sequence T GAP t T OEH AGC Gap Pulse t T OET Preliminary ...
Page 88
... PIC12F635/PIC16F636/639 FIGURE 11-6: OUTPUT ENABLE FILTER TIMING EXAMPLE (DETAILED) 3.5 ms Low Current T AGC Standby (AGC settling time) Mode T STAB (AFE Stabilization) Legend AGC stabilization time AGC T = Time element of pulse AGC stabilization gap GAP T = Minimum output enable filter high time OEH T = Minimum output enable filter low time ...
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... OET - or T > T OEL OET • A Soft Reset SPI command is received. © 2005 Microchip Technology Inc. PIC12F635/PIC16F636/639 If the filter resets due to a long high (T high-pulse timer will not begin timing again until after a gap of T and another low-to-high transition occurs OET the demodulator output ...
Page 90
... PIC12F635/PIC16F636/639 TABLE 11-2: INPUT SENSITIVITY VS. MODULATED SIGNAL STRENGTH SETTING (AGCSIG <7>) AGCSIG<7> (Config. Register 5) Disabled – the AFE passes signal of any amplitude level it is capable of 0 detecting (demodulated data and carrier clock). Enabled – No output until AGC Status = 1 (i.e (demodulated data and carrier clock). ...
Page 91
... The 75% setting can reduce the bit errors caused by noise, but gives the least demodulation sensitivity. See Table 11-3 for minimum modulation depth requirement settings. © 2005 Microchip Technology Inc. PIC12F635/PIC16F636/639 TABLE 11-3: SETTING FOR MINIMUM MODULATION DEPTH REQUIREMENT MODMIN Bits (Config ...
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... PIC12F635/PIC16F636/639 FIGURE 11-7: MODULATION DEPTH EXAMPLES (a) Modulation Depth Definition Amplitude (b) LFDATA Output vs. Input vs. Minimum Modulation Depth Setting Amplitude Amplitude 0 DS41232B-page 90 Modulation Depth (%) = Coil Input Strength PP Modulation Depth (%) = t Input signal with modulation depth = 30% Demodulated LFDATA Output when MODMIN Setting = 25% (LFDATA output = toggled) ...
Page 93
... Configuration Register 5 1 Configuration Register 6 1 (Column Parity Register) © 2005 Microchip Technology Inc. PIC12F635/PIC16F636/639 11.25 Error Detection of AFE Configuration Register Data The AFE's Configuration registers are volatile memory. Therefore, the contents of the registers can be corrupted or cleared by any electrical incidence such as battery disconnect ...
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... PIC12F635/PIC16F636/639 11.26 Factory Calibration Microchip calibrates the AFE to reduce the device-to- device variation in standby current, internal timing and sensitivity, as well as channel-to-channel sensitivity variation. 11.27 De-Q’ing of Antenna Circuit When the transponder is close to the base station, the transponder coil may develop coil voltage higher than ...
Page 95
... Register 1 (Register 11-2) for more details. 11.31.1 DEMODULATOR OUTPUT The demodulator output is the default configuration of the output selection. This is the output of an envelope detection circuit. See Figure 11-9 for the demodulator output. © 2005 Microchip Technology Inc. PIC12F635/PIC16F636/639 ) For a clean data output or to save operating power, the input channels can be individually enabled or disabled ...
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... PIC12F635/PIC16F636/639 Case I. When Output Enable Filter is disabled: Demodulated output is available immediately after the AGC stabilization time (T ). Figure 11-10 shows an example of demodulated output when the Output Enable Filter is disabled. AGC FIGURE 11-10: INPUT SIGNAL AND DEMODULATOR OUTPUT WHEN THE OUTPUT ENABLE FILTER IS DISABLED ...
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... FIGURE 11-12: NO DEMODULATOR OUTPUT (WHEN OUTPUT ENABLE FILTER IS ENABLED BUT INPUT DOES NOT MEET FILTER TIMING REQUIREMENTS) Input Signal © 2005 Microchip Technology Inc. PIC12F635/PIC16F636/639 No LFDATA Output Preliminary DS41232B-page 95 ...
Page 98
... PIC12F635/PIC16F636/639 11.31.2 CARRIER CLOCK OUTPUT When the Carrier Clock output is selected, the LFDATA output is a square pulse of the input carrier clock and available as soon as the AGC stabilization time (T completed. There are two Configuration register options for the carrier clock output: (a) clock divide-by one or (b) clock divide-by four, depending on bit DATOUT< ...
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... FIGURE 11-13: CARRIER CLOCK OUTPUT EXAMPLES (A) CARRIER CLOCK OUTPUT WITH CARRIER/1 OPTION Carrier Clock Output Carrier Input (B) CARRIER CLOCK OUTPUT WITH CARRIER/4 OPTION Carrier Clock Output Carrier Input © 2005 Microchip Technology Inc. PIC12F635/PIC16F636/639 Preliminary DS41232B-page 97 ...
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... PIC12F635/PIC16F636/639 11.31.3 RECEIVED SIGNAL STRENGTH INDICATOR (RSSI) OUTPUT An analog current is available at the LFDATA pin when the Received Signal Strength Indicator (RSSI) output is selected for the AFE’s Configuration register. The analog current is linearly proportional to the input signal strength (see Figure 11-15). ...
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... FIGURE 11-15: RSSI OUTPUT CURRENT VS. INPUT SIGNAL LEVEL EXAMPLE © 2005 Microchip Technology Inc. PIC12F635/PIC16F636/639 Input Voltage ( Preliminary DS41232B-page 99 ...
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... PIC12F635/PIC16F636/639 11.31.3.1 ANALOG-TO-DIGITAL DATA CONVERSION OF RSSI SIGNAL The AFE’s RSSI output is an analog current. It needs an external analog-to-digital (ADC) data conversion device for digitized output. The ADC data conversion can be accomplished by using a stand-alone external ADC device or by firmware utilizing MCU's internal comparator along with a few external resistors and a capacitor ...
Page 103
... Clock in 16-bit SPI Write sequence - command, address, data and parity bit. • command, address, data and parity bit 5. Change LFDATA/RSSI/CCLK/SDIO connected pin to input. 6. Raise CS to complete the SPI Write. 7. Change SCLK/ALERT back to input. © 2005 Microchip Technology Inc. PIC12F635/PIC16F636/639 16 Clocks for Write Command, Address and Data 1/F SCLK Preliminary ...
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... PIC12F635/PIC16F636/639 FIGURE 11-18: SPI READ SEQUENCE Clocks for Read Command, T CSSC Address and Dummy Data T HI SCLK/ALERT MSb SCLK ALERT 1/F (input) (output LFDATA/RSSI/ CCLK/SDIO 3 SDI LFDATA (input) (output) MCU SPI Read Details: 1. Drive the AFE’s open collector ALERT output low. ...
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... Note: ‘P’ denotes the row parity bit (odd parity) for the respective data byte. © 2005 Microchip Technology Inc. PIC12F635/PIC16F636/639 The AFE operates in SPI mode 0,0. In mode 0,0 the clock idles in the low state (Figure 11-19). SDI data is loaded into the AFE on the rising edge of SCLK and SDO data is clocked out on the falling edge of SCLK ...
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... PIC12F635/PIC16F636/639 FIGURE 11-19: DETAILED SPI INTERFACE TIMING (AFE SCLK MSb SDIO Command 11.32.2.1 Clamp On Command This command results in activating (turning on) the modulation transistors of all enabled channels; channels enabled in Configuration Register 0 (Register 11-1). 11.32.2.2 Clamp Off Command This command results in de-activating (turning off) the modulation transistors of all channels ...
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... R0PAR: Register Parity bit – set/cleared so the 9-bit register contains odd parity – an odd number of set bits Legend Readable bit W = Writable bit - n = Value at POR ‘1’ = Bit is set © 2005 Microchip Technology Inc. PIC12F635/PIC16F636/639 Bit 7 Bit 6 Bit 5 Bit 4 OEL ALRTIND Channel X Tuning Capacitor ...
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... PIC12F635/PIC16F636/639 REGISTER 11-2: CONFIGURATION REGISTER 1 (ADDRESS: 0001) R/W-0 R/W-0 DATOUT1 DATOUT0 LCXTUN5 bit 8 bit 8-7 DATOUT<1:0>: LFDATA Output type bit 00 = Demodulated output 01 = Carrier Clock output 10 = RSSI output 11 = RSSI output bit 6-1 LCXTUN<5:0>: LCX Tuning Capacitance bit 000000 =+0 pF (Default) : 111111 =+63 pF bit 0 R1PAR: Register Parity Bit – ...
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... R4PAR: Register Parity bit – set/cleared so the 9-bit register contains odd parity – an odd number of set bits Note 1: Assured monotonic increment (or decrement) by design. Legend Readable bit W = Writable bit - n = Value at POR ‘1’ = Bit is set © 2005 Microchip Technology Inc. PIC12F635/PIC16F636/639 R/W-0 R/W-0 R/W-0 R/W-0 LCZTUN4 LCZTUN3 LCZTUN2 U = Unimplemented bit, read as ‘ ...
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... PIC12F635/PIC16F636/639 REGISTER 11-6: CONFIGURATION REGISTER 5 (ADDRESS: 0101) R/W-0 R/W-0 AUTOCHSEL AGCSIG bit 8 bit 8 AUTOCHSEL: Auto Channel Select bit 1 = Enabled – AFE selects channel(s) that has demodulator output “high” at the end of T channel(s). AFE 0 = Disabled – follows channel enable/disable bits defined in Register 0 ...
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... W = Writable bit - n = Value at POR ‘1’ = Bit is set See Table 11-7 for the bit conditions of the AFE Status register after various SPI commands and the AFE Power-on Reset. © 2005 Microchip Technology Inc. PIC12F635/PIC16F636/639 R-0 R-0 R-0 CHXACT AGCACT WAKEZ WAKEY ...
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... PIC12F635/PIC16F636/639 TABLE 11-7: AFE STATUS REGISTER BIT CONDITION (AFTER POWER-ON RESET AND VARIOUS SPI COMMANDS) Bit 8 Condition CHZACT CHYACT CHXACT AGCACT WAKEZ WAKEY WAKEX ALARM POR 0 Read Command u (STATUS Register only) Sleep Command u (1) Soft Reset Executed 0 Legend unchanged Note 1: See Section 11.20 “Soft Reset” and Section 11.32.2.4 “Soft Reset Command” for the condition of Soft Reset execution ...
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... SPECIAL FEATURES OF THE CPU The PIC12F635/PIC16F636/639 has a host of features intended to maximize system reliability, minimize cost through elimination of external components, provide power saving features and offer code protection. These features are: • Reset - Power-on Reset (POR) - Wake-up Reset (WUR) - Power-up Timer (PWRT) ...
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... PIC12F635/PIC16F636/639 12.1 Configuration Word Bits The Configuration Word bits can be programmed (read as ‘0’), or left unprogrammed (read as ‘1’) to select various device configurations as shown in Register 12-1. These bits are mapped in program memory location 2007h. REGISTER 12-1: CONFIG – CONFIGURATION WORD (ADDRESS: 2007h) ...
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... Reset The PIC12F635/PIC16F636/639 differentiates between various kinds of Reset: a) Power-on Reset (POR) b) Wake-up Reset (WUR) c) WDT Reset during normal operation d) WDT Reset during Sleep e) MCLR Reset during normal operation f) MCLR Reset during Sleep g) Brown-out Detect (BOD) Some registers are not affected in any Reset condition; ...
Page 116
... The WUR bit in PCON will be cleared to ‘0’. DS41232B-page 114 12.5 MCLR PIC12F635/PIC16F636/639 has a noise filter in the DD MCLR Reset path. The filter will ignore small pulses. It should be noted that a WDT Reset does not drive MCLR pin low. See Figure 12-2 for the recommended MCLR circuit ...
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... V DD Internal Reset Note 1: Nominal 64 ms delay only if PWRTE bit is programmed to ‘0’. © 2005 Microchip Technology Inc. PIC12F635/PIC16F636/639 On any Reset (Power-on, Brown-out Detect, Watchdog Timer, etc.), the chip will remain in Reset until V above V (see Figure 12-3). The Power-up Timer BOD will now be invoked, if enabled and will keep the chip in Reset an additional nominal 64 ms ...
Page 118
... Then bringing MCLR high will begin execution immediately (see Figure 12-5). This is useful for testing purposes or to synchronize more than one PIC12F635/PIC16F636/ 639 device operating in parallel. Table 12-5 shows the Reset conditions for some special registers, while Table 12-4 shows the Reset conditions for all the registers ...
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... POR BOD WUR Legend unchanged unknown © 2005 Microchip Technology Inc. PIC12F635/PIC16F636/639 PD Condition Power-on Reset 1 Brown-out Detect 1 WDT Reset u WDT Wake-up 0 MCLR Reset during normal operation u MCLR Reset during Sleep 0 Wake-up Reset during Sleep 0 Brown-out Detect during Sleep 1 Preliminary DS41232B-page 117 ...
Page 120
... PIC12F635/PIC16F636/639 FIGURE 12-4: TIME-OUT SEQUENCE ON POWER-UP (DELAYED MCLR MCLR Internal POR PWRT Time-out OST Time-out Internal Reset FIGURE 12-5: TIME-OUT SEQUENCE ON POWER-UP (DELAYED MCLR MCLR Internal POR PWRT Time-out OST Time-out Internal Reset FIGURE 12-6: TIME-OUT SEQUENCE ON POWER-UP (MCLR WITH MCLR ...
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... See Table 12-5 for Reset value for specific condition Reset was due to brown-out, then bit All other Resets will cause bit PIC16F636/639 only. © 2005 Microchip Technology Inc. PIC12F635/PIC16F636/639 MCLR Reset WDT Reset (1) Brown-out Detect Wake-up Reset uuuu uuuu xxxx xxxx ...
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... PIC12F635/PIC16F636/639 TABLE 12-5: INITIALIZATION CONDITION FOR SPECIAL REGISTERS Condition Power-on Reset MCLR Reset during normal operation MCLR Reset during Sleep WDT Reset WDT Wake-up Brown-out Detect Interrupt Wake-up from Sleep Wake-up Reset Legend unchanged unknown, – = unimplemented bit, reads as ‘0’. ...
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... Interrupts The PIC12F635/PIC16F636/639 has 8 sources of interrupt: • External Interrupt RA2/INT • Timer0 Overflow Interrupt • PORTA Change Interrupts • 2 Comparator Interrupts • Timer1 Overflow Interrupt • EEPROM Data Write Interrupt • Fail-Safe Clock Monitor Interrupt The Interrupt Control register (INTCON) and Peripheral Interrupt Request Register 1 (PIR1) record individual interrupt requests in flag bits ...
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... PIC12F635/PIC16F636/639 12.9.2 TMR0 INTERRUPT An overflow (FFh 00h) in the TMR0 register will set the T0IF (INTCON<2>) bit. The interrupt can be enabled/disabled by setting/clearing T0IE (INTCON<5>) bit. See Section 5.0 “Timer0 Module” for operation of the Timer0 module. FIGURE 12-7: INTERRUPT LOGIC IOC-RA0 IOCA0 ...
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... PIR1 EEIF LVDIF 8Ch PIE1 EEIE LVDIE Legend unknown unchanged, — = unimplemented, read as ‘0’ value depends upon condition. Shaded cells are not used by the interrupt module. Note 1: PIC16F636/639 only. © 2005 Microchip Technology Inc. PIC12F635/PIC16F636/639 (1) (2) Interrupt Latency Inst ( — ...
Page 126
... W and Status registers). This must be implemented in software. Since the lower 16 bytes of all banks are common in the PIC12F635/PIC16F636/639 (see Figure 2-2), temporary holding registers, W_TEMP and STATUS_TEMP, should be placed in here. These 16 locations do not require banking and therefore, make it easier to context save and restore ...
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... Watchdog Timer (WDT) The PIC12F635/PIC16F636/639 WDT is code and functionally compatible with other PIC16F WDT modules and adds a 16-bit prescaler to the WDT. This allows the user to have a scaler value for the WDT and TMR0 at the same time. In addition, the WDT time-out value can be extended to 268 seconds ...
Page 128
... PIC12F635/PIC16F636/639 REGISTER 12-2: WDTCON – WATCHDOG TIMER CONTROL REGISTER (ADDRESS: 18h) U-0 U-0 — bit 7 bit 7-5 Unimplemented: Read as ‘0’ bit 4-1 WDTPS<3:0>: Watchdog Timer Period Select bits Bit Value = Prescale Rate 0000 = 1:32 0001 = 1:64 0010 = 1:128 0011 = 1:256 ...
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... EEPROM write operation completion. 4. Comparator output changes state. 5. Interrupt-on-change. © 2005 Microchip Technology Inc. PIC12F635/PIC16F636/639 6. External Interrupt from INT pin. Other peripherals cannot generate interrupts, since during Sleep, no on-chip clocks are present. When the SLEEP instruction is being executed, the next instruction ( prefetched. For the device to wake-up through an interrupt event, the corresponding interrupt enable bit must be set (enabled) ...
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... PIC12F635/PIC16F636/639 FIGURE 12-10: WAKE-UP FROM SLEEP THROUGH INTERRUPT OSC1 (4) CLKOUT INT pin INTF Flag (INTCON<1>) GIE bit (INTCON<7>) INSTRUCTION FLOW Instruction Inst( Inst(PC) = Sleep Fetched Instruction Sleep Inst(PC – 1) Executed Note 1: XT Oscillator mode assumed 1024 T (drawing not to scale). This delay does not apply to EC and RC Oscillator modes. ...
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... In-Circuit Serial Programming The PIC12F635/PIC16F636/639 microcontrollers can be serially programmed while in the end application circuit. This is simply done with two lines for clock and data and three other lines for: • Power • Ground • Programming Voltage This allows customers to manufacture boards with unprogrammed devices and then program the microcontroller just before shipping the product ...
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... PIC12F635/PIC16F636/639 NOTES: DS41232B-page 130 Preliminary © 2005 Microchip Technology Inc. ...
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... INSTRUCTION SET SUMMARY The PIC12F635/PIC16F636/639 instruction set is highly orthogonal and is comprised of three basic categories: • Byte-oriented operations • Bit-oriented operations • Literal and control operations Each PIC16FXXX instruction is a 14-bit word divided into an opcode, which specifies the instruction type and one or more operands, which further specify the operation of the instruction ...
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... PIC12F635/PIC16F636/639 TABLE 13-2: PIC12F635/PIC16F636/639 INSTRUCTION SET Mnemonic, Description Operands BYTE-ORIENTED FILE REGISTER OPERATIONS f, d Add W and f ADDWF f, d AND W with f ANDWF f Clear f CLRF - Clear W CLRW f, d Complement f COMF f, d Decrement f DECF f, d Decrement f, Skip if 0 DECFSZ f, d Increment f INCF f, d Increment f, Skip if 0 ...
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... Description: AND the W register with register ‘f’. If ‘d’ is ‘0’, the result is stored in the W register. If ‘d’ is ‘1’, the result is stored back in register ‘f’. © 2005 Microchip Technology Inc. PIC12F635/PIC16F636/639 BCF Syntax: Operands: Operation: Status Affected: Description: ...
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... PIC12F635/PIC16F636/639 CALL Call Subroutine Syntax: [ label ] CALL k Operands 2047 Operation: (PC)+ 1 TOS, k PC<10:0>, (PCLATH<4:3>) PC<12:11> Status Affected: None Description: Call subroutine. First, return address ( pushed onto the stack. The eleven-bit immediate address is loaded into PC bits <10:0>. The upper bits of the PC are loaded from PCLATH ...
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... Description: The contents of register ‘f’ are incremented. If ‘d’ is ‘0’, the result is placed in the W register. If ‘d’ is ‘1’, the result is placed back in register ‘f’. © 2005 Microchip Technology Inc. PIC12F635/PIC16F636/639 INCFSZ Increment f, Skip if 0 Syntax: [ label ] Operands: 0 ...
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... PIC12F635/PIC16F636/639 MOVF Move f Syntax: [ label ] MOVF f,d Operands 127 d [0,1] Operation: (f) (dest) Status Affected: Z Encoding: 00 1000 Description: The contents of register ‘f’ are moved to a destination dependent upon the status of ‘d’. If ‘d’ destination is W register the destination is file register ‘f’ ...
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... RETLW k2 ; • • • RETLW kn ; End of table Before Instruction W = 0x07 After Instruction W = value of k8 © 2005 Microchip Technology Inc. PIC12F635/PIC16F636/639 RETURN Syntax: Operands: Operation: Status Affected: Description: 0000 1001 RLF Syntax: Operands: Operation: Status Affected: Encoding: kkkk kkkk Description: ...
Page 140
... PIC12F635/PIC16F636/639 RRF Rotate Right f through Carry Syntax: [ label ] RRF f,d Operands 127 d [0,1] Operation: See description below Status Affected: C Description: The contents of register ‘f’ are rotated one bit to the right through the CARRY flag. If ‘d’ is ‘0’, the result is placed in the W register. If ‘ ...
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... Status Affected: Z Description: Exclusive OR the contents of the W register with register ‘f’. If ‘d’ is ‘0’, the result is stored in the W register. If ‘d’ is ‘1’, the result is stored back in register ‘f’. © 2005 Microchip Technology Inc. PIC12F635/PIC16F636/639 f,d Preliminary DS41232B-page 139 ...
Page 142
... PIC12F635/PIC16F636/639 NOTES: DS41232B-page 140 Preliminary © 2005 Microchip Technology Inc. ...
Page 143
... CAN ® - PowerSmart - Analog © 2005 Microchip Technology Inc. PIC12F635/PIC16F636/639 14.1 MPLAB Integrated Development Environment Software The MPLAB IDE software brings an ease of software development previously unseen in the 8/16-bit micro- controller market. The MPLAB IDE is a Windows based application that contains: • ...
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... PIC12F635/PIC16F636/639 14.3 MPLAB C17 and MPLAB C18 C Compilers The MPLAB C17 and MPLAB C18 Code Development Systems are complete ANSI C compilers for Microchip’s PIC17CXXX and PIC18CXXX family of microcontrol- lers. These compilers provide powerful integration capabilities, superior code optimization and ease of use not found with other compilers ...
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... The PC platform and Microsoft Windows 32-bit operating system were chosen to best make these features available in a simple, unified application. © 2005 Microchip Technology Inc. PIC12F635/PIC16F636/639 14.11 MPLAB ICD 2 In-Circuit Debugger Microchip’s In-Circuit Debugger, MPLAB ICD powerful, low-cost, connecting to the host PC via an RS-232 or high-speed USB interface ...
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... PIC12F635/PIC16F636/639 14.14 PICSTART Plus Development Programmer The PICSTART Plus development programmer is an easy-to-use, low-cost, prototype programmer. It con- nects to the PC via a COM (RS-232) port. MPLAB Integrated Development Environment software makes using the programmer simple and efficient. The PICSTART Plus development programmer supports most PICmicro devices pins ...
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... Microcontrollers” Handbook and a USB interface cable. Supports all current 8/14-pin Flash PIC microcontrollers, as well as many future planned devices. © 2005 Microchip Technology Inc. PIC12F635/PIC16F636/639 14.24 PICDEM USB PIC16C7X5 Demonstration Board The PICDEM USB Demonstration Board shows off the capabilities of the PIC16C745 and PIC16C765 USB A microcontrollers ...
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... PIC12F635/PIC16F636/639 NOTES: DS41232B-page 146 Preliminary © 2005 Microchip Technology Inc. ...
Page 149
... Maximum LC Input Voltage (LCX, LCY, LCZ) Maximum LC Input Voltage (LCX, LCY, LCZ) Maximum Input Current (rms) into device per LC Channel Human Body ESD rating ........................................................................................................................ 4000 (min.) V Machine Model ESD rating ...................................................................................................................... 400 (min.) V Note 1: Power dissipation for PIC12F635/PIC16F636/639 (AFE section not included) is calculated as follows: - ∑ ∑ {( ...
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... PIC12F635/PIC16F636/639 FIGURE 15-1: PIC12F635/PIC16F636 VOLTAGE-FREQUENCY GRAPH, -40°C 5.5 5.0 4.5 4 (Volts) 3.5 3.0 2.5 2.0 0 Note 1: The shaded region indicates the permissible combinations of voltage and frequency. FIGURE 15-2: PIC16F639 VOLTAGE-FREQUENCY GRAPH, -40°C 5.5 5.0 4.5 4 (Volts) 3.6 3.0 2.5 2.0 0 Note 1: The shaded region indicates the permissible combinations of voltage and frequency. ...
Page 151
... DC Characteristics: PIC12F635/PIC16F636-I (Industrial) PIC12F635/PIC16F636-E (Extended) DC CHARACTERISTICS Param Sym Characteristic No. V Supply Voltage DD D001 D001C D001D D002 V RAM Data Retention DR (1) Voltage D003 V V Start Voltage to POR DD ensure internal Power-on Reset signal D004 S V Rise Rate to ensure VDD DD internal Power-on Reset ...
Page 152
... PIC12F635/PIC16F636/639 15.2 DC Characteristics: PIC12F635/PIC16F636-I (Industrial) DC CHARACTERISTICS Param Sym Device Characteristics No. (1,2) D010 I Supply Current DD D011 D012 D013 D014 D015 D016 D017 D018 Legend: TBD = To Be Determined † Data in ‘Typ’ column is at 5.0V unless otherwise stated. These parameters are for design guidance only and are not tested ...
Page 153
... DC Characteristics: PIC12F635/PIC16F636-I (Industrial) (Continued) DC CHARACTERISTICS Param Sym Device Characteristics No. D020 I Power-down Base PD (4) Current D021 IWDT D022A IBOD D022B ILVD D023 ICMP D024 IV REF D025 IT1OSC Legend: TBD = To Be Determined † Data in ‘Typ’ column is at 5.0V unless otherwise stated. These parameters are for design guidance only and are not tested ...
Page 154
... PIC12F635/PIC16F636/639 15.3 DC Characteristics: PIC12F635/PIC16F636-E (Extended) DC CHARACTERISTICS Param Sym Device Characteristics No. (1,2) D010E I Supply Current DD D011E D012E D013E D014E D015E D016E D017E D018E Legend: TBD = To Be Determined † Data in ‘Typ’ column is at 5.0V unless otherwise stated. These parameters are for design guidance only and are not tested ...
Page 155
... DC Characteristics: PIC12F635/PIC16F636-E (Extended) (Continued) DC CHARACTERISTICS Param Sym Device Characteristics No. D020 I Power-down Base PD (4) Current D021 IWDT D022A IBOD D022B ILVD D023 ICMP D024 IV REF D025 IT1OSC Legend: TBD = To Be Determined † Data in ‘Typ’ column is at 5.0V unless otherwise stated. These parameters are for design guidance only and are not tested ...
Page 156
... PIC12F635/PIC16F636/639 15.4 DC Characteristics: PIC12F635/PIC16F636-I (Industrial) PIC12F635/PIC16F636-E (Extended) DC CHARACTERISTICS Param Sym Characteristic No. V Input Low Voltage IL I/O ports: D030 with TTL buffer D030A D031 with Schmitt Trigger buffer D032 MCLR, OSC1 (RC mode) D033 OSC1 (XT and LP modes) (1) D033A OSC1 (HS mode) V Input High Voltage ...
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... DC Characteristics: PIC12F635/PIC16F636-I (Industrial) PIC12F635/PIC16F636-E (Extended) (Continued) DC CHARACTERISTICS Param Sym Characteristic No. V Output High Voltage OH D090 I/O ports D092 OSC2/CLKOUT (RC mode) D100 I Ultra Low-power Wake-up ULP Current Capacitive Loading Specs on Output Pins D100 COSC2 OSC2 pin D101 C All I/O pins IO Data EEPROM Memory ...
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... PIC12F635/PIC16F636/639 15.5 DC Characteristics: PIC16F639-I (Industrial), PIC16F639-E (Extended) DC CHARACTERISTICS Param Sym Characteristic No. D001 V Supply Voltage DD D001A V Supply Voltage (AFE) DDT D002 V RAM Data Retention DR (1) Voltage D003 V V Start Voltage to POR DD ensure internal Power-on Reset signal D003A V V Start Voltage (AFE) PORT ...
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... The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with the part in Sleep mode, with all I/O pins in high-impedance state and tied to V © 2005 Microchip Technology Inc. PIC12F635/PIC16F636/639 Standard Operating Conditions (unless otherwise stated) Operating temperature -40° ...
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... PIC12F635/PIC16F636/639 15.7 DC Characteristics: PIC16F639-E (Extended) DC CHARACTERISTICS Param Sym Device Characteristics No. (1,2) D010E I Supply Current DD D011E D012E D013E D014E D015E D016E D017E D020 I Power-down Base Current PD D021 IWDT D022A IBOD D022B ILVD D023 ICMP D024 IV REF D025 IT1OSC D026 I Active Current of AFE only ...
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... The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. Higher leakage current may be measured at different input voltages. 4: See Section 9.4.1 “Using the Data EEPROM” for additional information © 2005 Microchip Technology Inc. PIC12F635/PIC16F636/639 Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C -40°C Supply Voltage 2 ...
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... PIC12F635/PIC16F636/639 15.8 DC Characteristics: PIC16F639-I (Industrial), PIC16F639-E (Extended) (Continued) DC CHARACTERISTICS Param Sym Characteristic No. V Output High Voltage OH D090 I/O ports D092 OSC2/CLKOUT (RC mode) Digital Output High Voltage D093 LFDATA/SDIO for Analog Front-End (AFE) Capacitive Loading Specs on Output Pins D100 COSC2 OSC2 pin ...
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... MCLR Uppercase letters and their meanings Fall H High I Invalid (High-impedance) L Low FIGURE 15-3: LOAD CONDITIONS Load Condition 1 pin Legend 464 for all pins for OSC2 output © 2005 Microchip Technology Inc. PIC12F635/PIC16F636/639 T Time osc OSC1 SCLK T0CKI t1 T1CKI Period R Rise V Valid ...
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... PIC12F635/PIC16F636/639 15.10 AC Characteristics: PIC12F635/PIC16F636/639 (Industrial, Extended) FIGURE 15-4: EXTERNAL CLOCK TIMING Q4 OSC1 CLKOUT TABLE 15-1: EXTERNAL CLOCK TIMING REQUIREMENTS Param Sym Characteristic No. F External CLKIN Frequency OSC (1) Oscillator Frequency 1 T External CLKIN Period OSC (1) Oscillator Period 2 T Instruction Cycle Time CY 3 TosL, ...
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... F and 0.01 F values in parallel are recommended. FIGURE 15-5: CLKOUT AND I/O TIMING Q4 OSC1 CLKOUT I/O pin (Input) I/O pin Old Value (Output) © 2005 Microchip Technology Inc. PIC12F635/PIC16F636/639 Freq Min Typ† Max Tolerance 1% — 8.00 TBD (1) 2% — ...
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... PIC12F635/PIC16F636/639 TABLE 15-3: CLKOUT AND I/O TIMING REQUIREMENTS Param Sym Characteristic No OSC1 to CLKOUT OSC1 to CLKOUT CLKOUT Rise Time CLKOUT Fall Time CLKOUT to Port Out Valid Port In Valid before CLKOUT Port In Hold after CLKOUT OSC1 (Q1 cycle) to Port Out Valid OSC1 (Q2 cycle) to Port Input ...
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... These parameters are characterized but not tested. † Data in ‘Typ’ column is at 5.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. © 2005 Microchip Technology Inc. PIC12F635/PIC16F636/639 (Device not in Brown-out Detect Time-out Min Typ† ...
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... PIC12F635/PIC16F636/639 FIGURE 15-8: TIMER0 AND TIMER1 EXTERNAL CLOCK TIMINGS T0CKI T1CKI TMR0 or TMR1 TABLE 15-5: TIMER0 AND TIMER1 EXTERNAL CLOCK REQUIREMENTS Param Sym Characteristic No. 40 T0CKI High Pulse Width T 41 T0CKI Low Pulse Width T 42 T0CKI Period T 45 T1CKI High Synchronous, No Prescaler ...
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... Absolute Accuracy Unit Resistor Value (R) (1) Settling Time * These parameters are characterized but not tested. Note 1: Settling time measured while VRR = 1 and VR<3:0> transitions from ‘0000’ to ‘1111‘. © 2005 Microchip Technology Inc. PIC12F635/PIC16F636/639 +125°C A Min Typ Max — 5.0 10 – ...
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... PIC12F635/PIC16F636/639 15.11 AC Characteristics: Analog Front-End for PIC16F639 (industrial, extended) AC CHARACTERISTICS Param Sym. Characteristic No Input Sensitivity SENSE V _ Coil de-Q’ing Voltage - Limiter (R ) must be active FLM R RF Limiter Turn-on Resistance FLM (LCX, LCY, LCZ) S Sensitivity Reduction ADJ V _ Minimum Modulation Depth IN MOD 75% ± ...
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... Required output enable filter high time must account for input path analog delays = T 2: Required output enable filter low time must account for input path analog delays (= T © 2005 Microchip Technology Inc. PIC12F635/PIC16F636/639 Standard Operating Conditions (unless otherwise stated) Supply Voltage 2. ...
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... PIC12F635/PIC16F636/639 15.11 AC Characteristics: Analog Front-End for PIC16F639 (industrial, extended) (Continued) AC CHARACTERISTICS Param Sym. Characteristic No. T Time element of pulse E T Minimum output enable filter high OEH time OEH (Bits Config0<7:6> Filter Disabled T Minimum output enable filter low OEL time OEL (Bits Config0<5:4>) ...
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... Note 1: Required output enable filter high time must account for input path analog delays = T 2: Required output enable filter low time must account for input path analog delays (= T © 2005 Microchip Technology Inc. PIC12F635/PIC16F636/639 Standard Operating Conditions (unless otherwise stated) Supply Voltage 2 ...
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... PIC12F635/PIC16F636/639 NOTES: DS41232B-page 172 Preliminary © 2005 Microchip Technology Inc. ...
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... DC AND AC CHARACTERISTICS GRAPHS AND TABLES Graphs and Tables are not available at this time. © 2005 Microchip Technology Inc. PIC12F635/PIC16F636/639 Preliminary DS41232B-page 173 ...
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... PIC12F635/PIC16F636/639 NOTES: DS41232B-page 174 Preliminary © 2005 Microchip Technology Inc. ...
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... Standard PICmicro device marking consists of Microchip part number, year code, week code and traceability code. For PICmicro device marking beyond this, certain price adders apply. Please check with your Microchip Sales Office. For QTP devices, any special marking adders are included in QTP price. © 2005 Microchip Technology Inc. PIC12F635/PIC16F636/639 Example 12F635/P 017 0510 ...
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... PIC12F635/PIC16F636/639 17.1 Package Marking Information (Continued) 14-Lead SOIC XXXXXXXXXXX XXXXXXXXXXX YYWWNNN 14-Lead TSSOP XXXXXXXX YYWW NNN 20-Lead SSOP XXXXXXXXXXX XXXXXXXXXXX YYWWNNN DS41232B-page 176 Example PIC16F636 -I/SL 0510017 Example F636/ST 0510 017 Example PIC16F639 -I/SS 0510017 Preliminary © 2005 Microchip Technology Inc. ...
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... Mold Draft Angle Bottom * Controlling Parameter § Significant Characteristic Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010” (0.254mm) per side. JEDEC Equivalent: MS-001 Drawing No. C04-018 © 2005 Microchip Technology Inc. PIC12F635/PIC16F636/639 Units ...
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... PIC12F635/PIC16F636/639 8-Lead Plastic Small Outline (SN) – Narrow, 150 mil Body (SOIC Dimension Limits Number of Pins Pitch Overall Height Molded Package Thickness Standoff § Overall Width Molded Package Width Overall Length Chamfer Distance Foot Length Foot Angle Lead Thickness Lead Width Mold Draft Angle Top ...
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... Plastic Dual Flat No Lead Package (MF) 6x5 mm Body (DFN-S) – Saw Singulated © 2005 Microchip Technology Inc. PIC12F635/PIC16F636/639 Preliminary DS41232B-page 179 ...
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... PIC12F635/PIC16F636/639 14-Lead Plastic Dual In-line (P) – 300 mil Body (PDIP Dimension Limits Number of Pins Pitch Top to Seating Plane Molded Package Thickness Base to Seating Plane Shoulder to Shoulder Width Molded Package Width Overall Length Tip to Seating Plane Lead Thickness Upper Lead Width Lower Lead Width Overall Row Spacing § ...
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... Mold Draft Angle Bottom * Controlling Parameter § Significant Characteristic Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010” (0.254mm) per side. JEDEC Equivalent: MS-012 Drawing No. C04-065 © 2005 Microchip Technology Inc. PIC12F635/PIC16F636/639 Units ...
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... PIC12F635/PIC16F636/639 14-Lead Plastic Thin Shrink Small Outline (ST) – 4.4 mm Body (TSSOP Dimension Limits Number of Pins Pitch Overall Height Molded Package Thickness Standoff § Overall Width Molded Package Width Molded Package Length Foot Length Foot Angle Lead Thickness Lead Width Mold Draft Angle Top ...
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... Lead Thickness Foot Angle Lead Width *Controlling Parameter Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" (0.254mm) per side. JEDEC Equivalent: MO-150 Drawing No. C04-072 © 2005 Microchip Technology Inc. PIC12F635/PIC16F636/639 Units INCHES MIN ...
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... PIC12F635/PIC16F636/639 NOTES: DS41232B-page 184 Preliminary © 2005 Microchip Technology Inc. ...
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... To register, access the Microchip web site at www.microchip.com, click on Customer Change Notification and follow the registration instructions. © 2005 Microchip Technology Inc. PIC12F635/PIC16F636/639 CUSTOMER SUPPORT Users of Microchip products can receive assistance through several channels: • Distributor or Representative • ...
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... Telephone: (_______) _________ - _________ Application (optional): Would you like a reply? Y Device: PIC12F635/PIC16F636/639 Questions: 1. What are the best features of this document? 2. How does this document meet your hardware and software development needs you find the organization of this document easy to follow? If not, why? 4 ...
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... APPENDIX A: DATA SHEET REVISION HISTORY Revision A This is a new data sheet. Revision B Added PIC16F639 to the data sheet. © 2005 Microchip Technology Inc. PIC12F635/PIC16F636/639 Preliminary DS41232B-page 187 ...
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... PIC12F635/PIC16F636/639 NOTES: DS41232B-page 188 Preliminary © 2005 Microchip Technology Inc. ...
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... B Block Diagrams Analog Input Model..................................................... 62 Ceramic Resonator Operation.................................... 31 Clock Source .............................................................. 29 Comparator C1 Output ............................................... 65 Comparator C2 Output ............................................... 66 Comparator I/O Operating Modes for PIC12F635 ...... 63 Comparator I/O Operating Modes for PIC16F636/639 .................................................. 64 Comparator Voltage Reference (CV External Clock Mode .................................................. 31 Fail-Safe Clock Monitor (FSCM)................................. 36 Functional (AFE)......................................................... 82 In-Circuit Serial Programming Connection ............... 129 Interrupt Logic ...
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... DC and AC Characteristics Graphs and Tables........................... 173 DC Characteristics Extended (PIC12F635/PIC16F636) .......................... 152 Extended (PIC16F639) ............................................. 158 Industrial (PIC12F635/PIC16F636)........................... 150 Industrial (PIC16F639) .............................................. 157 Industrial/Extended (PIC12F635/PIC16F636) .. 149, 154 Industrial/Extended (PIC16F639)...................... 156, 159 Demonstration Boards PICDEM 1 ................................................................. 144 PICDEM 17 ............................................................... 145 PICDEM 18R ............................................................ 145 PICDEM 2 Plus ......................................................... 144 PICDEM 3 ................................................................. 144 PICDEM 4 ...
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... Precision Internal Oscillator Parameters .......................... 163 Prescaler Shared WDT/Timer0................................................... 55 Switching Prescaler Assignment ................................ 55 PRO MATE II Universal Device Programmer ................... 143 Product Identification ........................................................ 193 Program Memory ................................................................ 11 Program Memory Map and Stack PIC12F635 ................................................................. 11 PIC16F636/639 .......................................................... 11 Programmable Low-Voltage Detect (PLVD) Module .......... 71 Programming, Device Instructions.................................... 131 R Reader Response............................................................. 186 Read-Modify-Write Operations ......................................... 131 Registers Analog Front-End (AFE) AFE Status Register 7 ...
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... Software Simulator (MPLAB SIM30)................................. 142 Special Function Registers (SFR)....................................... 12 Maps PIC12F635.......................................................... 13 PIC16F636/639................................................... 14 Summary PIC12F635, Bank 0............................................. 15 PIC12F635, Bank 1............................................. 16 PIC12F635/PIC16F636/639, Bank 2 .................. 19 PIC16F636/639, Bank 0...................................... 17 PIC16F636/639, Bank 1...................................... 18 SPI Timing Analog Front-End (AFE) for PIC16F639 ................... 171 Status Register IRP Bit ......................................................................... 20 RP Bits ........................................................................ 20 T Time-out Sequence ...
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... SSOP (209 mil, 20-pin TSSOP (4.4 mm, 14-pin) Pattern 3-Digit Pattern Code for QTP (blank otherwise) © 2005 Microchip Technology Inc. PIC12F635/PIC16F636/639 XXX Examples: Pattern a) PIC12F635-E/P 301 = Extended Temp., PDIP package, 20 MHz, QTP pattern #301 b) PIC12F635-I/S = Industrial Temp., SOIC package, 20 MHz range DD range DD range DD Preliminary ...
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... Taiwan - Kaohsiung Tel: 886-7-536-4818 Fax: 886-7-536-4803 Taiwan - Taipei Tel: 886-2-2500-6610 Fax: 886-2-2508-0102 Taiwan - Hsinchu Tel: 886-3-572-9526 Fax: 886-3-572-6459 Preliminary © 2005 Microchip Technology Inc. EUROPE Austria - Weis Tel: 43-7242-2244-399 Fax: 43-7242-2244-393 Denmark - Ballerup Tel: 45-4450-2828 Fax: 45-4485-2829 France - Massy Tel: 33-1-69-53-63-20 ...