AT89S51-24JU Atmel, AT89S51-24JU Datasheet - Page 13
![IC MCU 4K FLASH 24MHZ 44-PLCC](/photos/6/70/67043/453-44-plcc_sml.jpg)
AT89S51-24JU
Manufacturer Part Number
AT89S51-24JU
Description
IC MCU 4K FLASH 24MHZ 44-PLCC
Manufacturer
Atmel
Series
89Sr
Datasheet
1.AT89S51-24JU.pdf
(31 pages)
Specifications of AT89S51-24JU
Core Processor
8051
Core Size
8-Bit
Speed
24MHz
Connectivity
UART/USART
Peripherals
WDT
Number Of I /o
32
Program Memory Size
4KB (4K x 8)
Program Memory Type
FLASH
Ram Size
128 x 8
Voltage - Supply (vcc/vdd)
4 V ~ 5.5 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
44-PLCC
Processor Series
AT89x
Core
8051
Data Bus Width
8 bit
Data Ram Size
128 B
Interface Type
UART
Maximum Clock Frequency
33 MHz
Number Of Programmable I/os
32
Number Of Timers
2
Operating Supply Voltage
4 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
PK51, CA51, A51, ULINK2
Development Tools By Supplier
AT89ISP
Minimum Operating Temperature
- 40 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Data Converters
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
AT89S51-24JU
Manufacturer:
ATMEL
Quantity:
13 888
Part Number:
AT89S51-24JU
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
12. Idle Mode
13. Power-down Mode
2487D–MICRO–6/08
Figure 11-2. External Clock Drive Configuration
In idle mode, the CPU puts itself to sleep while all the on-chip peripherals remain active. The
mode is invoked by software. The content of the on-chip RAM and all the special function regis-
ters remain unchanged during this mode. The idle mode can be terminated by any enabled
interrupt or by a hardware reset.
Note that when idle mode is terminated by a hardware reset, the device normally resumes pro-
gram execution from where it left off, up to two machine cycles before the internal reset
algorithm takes control. On-chip hardware inhibits access to internal RAM in this event, but
access to the port pins is not inhibited. To eliminate the possibility of an unexpected write to a
port pin when idle mode is terminated by a reset, the instruction following the one that invokes
idle mode should not write to a port pin or to external memory.
In the Power-down mode, the oscillator is stopped, and the instruction that invokes Power-down
is the last instruction executed. The on-chip RAM and Special Function Registers retain their
values until the Power-down mode is terminated. Exit from Power-down mode can be initiated
either by a hardware reset or by activation of an enabled external interrupt (INT0 or INT1). Reset
redefines the SFRs but does not change the on-chip RAM. The reset should not be activated
before V
the oscillator to restart and stabilize.
Table 13-1.
Mode
Idle
Idle
Power-down
Power-down
CC
is restored to its normal operating level and must be held active long enough to allow
Status of External Pins During Idle and Power-down Modes
Program Memory
Internal
External
Internal
External
OSCILLATOR
EXTERNAL
SIGNAL
ALE
NC
1
1
0
0
PSEN
1
1
0
0
XTAL2
XTAL1
GND
PORT0
Float
Float
Data
Data
PORT1
Data
Data
Data
Data
Address
PORT2
Data
Data
Data
AT89S51
PORT3
Data
Data
Data
Data
13