ATTINY45V-10MU Atmel, ATTINY45V-10MU Datasheet - Page 52

• Manufacturer Part Number: ATTINY45V-10MU
• Description: IC AVR MCU FLASH 4K 10MHZ 20MLF
• Manufacturer: Atmel
• Series: AVR® ATtinyr

Specifications of ATTINY45V-10MU

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 10MHz
• Connectivity: USI
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 6
• Program Memory Size: 4KB (2K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 20-MLF®, QFN
• Processor Series: ATTINY4x
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 256 B
• Interface Type: USI
• Maximum Clock Frequency: 10 MHz
• Number Of Programmable I/os: 6
• Number Of Timers: 2
• Operating Supply Voltage: 1.8 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 4 Channel
• Package: 20MLF EP
• Device Core: AVR
• Family Name: ATtiny
• Maximum Speed: 10 MHz
• For Use With: ATSTK600-DIP40 - STK600 SOCKET/ADAPTER 40-PDIPATAVRBC100 - REF DESIGN KIT BATTERY CHARGER770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAGATAVRDRAGON - KIT DRAGON 32KB FLASH MEM AVRATAVRISP2 - PROGRAMMER AVR IN SYSTEMATJTAGICE2 - AVR ON-CHIP D-BUG SYSTEM
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

9.2.2
9.3
9.3.1
52
Register Description
ATtiny25/45/85
Pin Change Interrupt Timing
MCUCR – MCU Control Register
An example of timing of a pin change interrupt is shown in
Figure 9-1.
The External Interrupt Control Register A contains control bits for interrupt sense control.
• Bits 1:0 – ISC0[1:0]: Interrupt Sense Control 0 Bit 1 and Bit 0
The External Interrupt 0 is activated by the external pin INT0 if the SREG I-flag and the corre-
sponding interrupt mask are set. The level and edges on the external INT0 pin that activate the
interrupt are defined in
If edge or toggle interrupt is selected, pulses that last longer than one clock period will generate
an interrupt. Shorter pulses are not guaranteed to generate an interrupt. If low level interrupt is
pcint_setflag
Bit
0x35
Read/Write
Initial Value
pcint_in_(0)
PCINT(0)
pcint_syn
pin_sync
pin_lat
PCINT(0)
PCIF
clk
clk
Timing of pin change interrupts
BODS
R
7
0
LE
pin_lat
Table
PUD
R/W
D
6
0
Q
9-2. The value on the INT0 pin is sampled before detecting edges.
pin_sync
PCINT(0) in PCMSK(x)
R/W
SE
5
0
SM1
R/W
4
0
pcint_in_(0)
SM0
R/W
3
0
0
x
clk
Figure
BODSE
R
2
0
9-1.
pcint_syn
ISC01
R/W
1
0
pcint_setflag
ISC00
R/W
0
0
2586M–AVR–07/10
MCUCR
PCIF