PIC16F685-I/P Microchip Technology, PIC16F685-I/P Datasheet - Page 208

• Manufacturer Part Number: PIC16F685-I/P
• Description: IC PIC MCU FLASH 4KX14 20DIP
• Manufacturer: Microchip Technology
• Series: PIC® 16Fr

Specifications of PIC16F685-I/P

• Program Memory Type: FLASH
• Program Memory Size: 7KB (4K x 14)
• Package / Case: 20-DIP (0.300", 7.62mm)
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 20MHz
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 18
• Eeprom Size: 256 x 8
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC16F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 256 B
• Interface Type: I2C/SPI/SSP/EUSART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 17
• Number Of Timers: 3
• Operating Supply Voltage: 2 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: Through Hole
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, DM163029, DV164120
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12-ch x 10-bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC162061 - HEADER INTRFC MPLAB ICD2 20PINAC164039 - MODULE SKT PROMATE II 20DIP/SOICDM163029 - BOARD PICDEM FOR MECHATRONICSACICE0203 - MPLABICE 20P 300 MIL ADAPTER
• Connectivity: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

PIC16F631/677/685/687/689/690
FIGURE 14-8:
TABLE 14-6:
DS41262C-page 206
INTCON
PIE1
PIE2
PIR1
PIR2
Legend:
INSTRUCTION FLOW
GIE bit
(INTCON<7>)
INTF flag
(INTCON<1>)
Name
CLKOUT
INT pin
OSC1
Note 1: INTF flag is sampled here (every Q1).
Instruction
Executed
Instruction
Fetched
PC
2: Asynchronous interrupt latency = 3-4 T
3: CLKOUT is available only in INTOSC and RC Oscillator modes.
4: For minimum width of INT pulse, refer to AC specifications in Section 17.0 “Electrical Specifications”.
5: INTF is enabled to be set any time during the Q4-Q1 cycles.
x = unknown, u = unchanged, — = unimplemented read as ‘0’, q = value depends upon condition.
Shaded cells are not used by the Interrupt module.
(3)
is the same whether Inst (PC) is a single cycle or a 2-cycle instruction.
OSFIE
OSFIF
Bit 7
GIE
—
—
SUMMARY OF INTERRUPT REGISTERS
Q1
Inst (PC – 1)
Inst (PC)
(1)
INT PIN INTERRUPT TIMING
Q2
PC
ADIE
Bit 6
PEIE
C2IE
ADIF
C2IF
Q3
(4)
Q4
(5)
RCIE
RCIF
Bit 5
T0IE
C1IE
C1IF
Q1
Inst (PC + 1)
Inst (PC)
Q2
(1)
INTE
TXIE
EEIE
EEIF
Bit 4
TXIF
PC + 1
Q3
CY
. Synchronous latency = 3 T
Preliminary
Q4
RABIE
SSPIE
SSPIF
Bit 3
—
—
Interrupt Latency
Q1
Dummy Cycle
CCP1IE
CCP1IF
Q2
PC + 1
Bit 2
T0IF
—
—
—
Q3
TMR2IE
TMR2IF
Q4
(2)
INTF
Bit 1
CY
—
—
, where T
Q1
Dummy Cycle
Inst (0004h)
TMR1IE
TMR1IF
Q2
RABIF
0004h
Bit 0
CY
—
—
= instruction cycle time. Latency
Q3
© 2006 Microchip Technology Inc.
Q4
0000 000x
-000 0000
0000 ----
-000 0000
0000 ----
POR, BOR
Value on
Q1
Inst (0005h)
Q2
Inst (0004h)
0005h
0000 000x
-000 0000
0000 ----
-000 0000
0000 ----
Value on
Q3
all other
Resets
Q4