PIC16F689-I/SO Microchip Technology, PIC16F689-I/SO Datasheet - Page 174
![IC PIC MCU FLASH 4KX14 20SOIC](/photos/6/64/66480/150-20-soic_sml.jpg)
PIC16F689-I/SO
Manufacturer Part Number
PIC16F689-I/SO
Description
IC PIC MCU FLASH 4KX14 20SOIC
Manufacturer
Microchip Technology
Series
PIC® 16Fr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PIC16F690DM-PCTLHS.pdf
(306 pages)
3.PIC16F677-IP.pdf
(2 pages)
4.PIC16F677-IP.pdf
(16 pages)
5.PIC16F677-ISO.pdf
(294 pages)
Specifications of PIC16F689-I/SO
Program Memory Type
FLASH
Program Memory Size
7KB (4K x 14)
Package / Case
20-SOIC (7.5mm Width)
Core Processor
PIC
Core Size
8-Bit
Speed
20MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, WDT
Number Of I /o
18
Eeprom Size
256 x 8
Ram Size
256 x 8
Voltage - Supply (vcc/vdd)
2 V ~ 5.5 V
Data Converters
A/D 12x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
PIC16F
Core
PIC
Data Bus Width
8 bit
Data Ram Size
256 B
Interface Type
I2C/SPI/SSP/EUSART
Maximum Clock Frequency
20 MHz
Number Of Programmable I/os
17
Number Of Timers
2
Operating Supply Voltage
2 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, DM163029, DM164120
Minimum Operating Temperature
- 40 C
On-chip Adc
12-ch x 10-bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
XLT20SO1-1 - SOCKET TRANS ICE 20DIP TO 20SOICXLT28SO-1 - SOCKET TRANSITION 28SOIC 300MILXLT18SO-1 - SOCKET TRANSITION 18SOIC 300MILAC162061 - HEADER INTRFC MPLAB ICD2 20PINAC164039 - MODULE SKT PROMATE II 20DIP/SOIC
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
- PIC16F616T-ISL PDF datasheet
- PIC16F690DM-PCTLHS PDF datasheet #2
- PIC16F677-IP PDF datasheet #3
- PIC16F677-IP PDF datasheet #4
- PIC16F677-ISO PDF datasheet #5
- Current page: 174 of 294
- Download datasheet (6Mb)
PIC16F631/677/685/687/689/690
FIGURE 12-12:
TABLE 12-8:
DS41262C-page 172
BAUDCTL ABDOVF
INTCON
PIE1
PIR1
RCREG
RCSTA
SPBRG
SPBRGH
TRISB
TXREG
TXSTA
Legend:
TX/CK pin
TX/CK pin
(SCKP = 0)
(SCKP = 1)
RX/DT
CREN bit
SREN bit
bit SREN
RCIF bit
(Interrupt)
Read
Note:
Write to
RXREG
Name
pin
x = unknown, – = unimplemented read as ‘0’. Shaded cells are not used for Synchronous Master Reception.
EUSART Receive Data Register
EUSART Transmit Data Register
‘0’
Timing diagram demonstrates Sync Master mode with bit SREN = 1 and bit BRGH = 0.
TRISB7
BRG15
CSRC
SPEN
BRG7
Bit 7
GIE
—
—
REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER RECEPTION
SYNCHRONOUS RECEPTION (MASTER MODE, SREN)
TRISB6
BRG14
RCIDL
BRG6
ADIE
PEIE
ADIF
Bit 6
RX9
TX9
bit 0
TRISB5
BRG13
SREN
BRG5
TXEN
RCIE
RCIF
Bit 5
T0IE
—
bit 1
TRISB4
BRG12
CREN
SCKP
BRG4
SYNC
INTE
Bit 4
TXIE
TXIF
bit 2
Preliminary
ADDEN
SENDB
BRG16
BRG11
RABIE
SSPIE
SSPIF
BRG3
Bit 3
bit 3
CCP1IE
CCP1IF
BRG10
BRGH
FERR
BRG2
Bit 2
T0IF
—
bit 4
TMR2IE
TMR2IF
OERR
TRMT
BRG1
BRG9
WUE
Bit 1
INTF
bit 5
TMR1IE
TMR1IF
ABDEN
RABIF
RX9D
BRG0
BRG8
TX9D
Bit 0
© 2006 Microchip Technology Inc.
bit 6
01-0 0-00
0000 000x
-000 0000
-000 0000
0000 0000
0000 000x
0000 0000
0000 0000
1111 ----
0000 0000
0000 0010
POR, BOR
Value on
bit 7
01-0 0-00
0000 000x
-000 0000
-000 0000
0000 0000
0000 000x
0000 0000
0000 0000
1111 ----
0000 0000
0000 0010
Value on
all other
Resets
‘0’
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