ATTINY44A-PU Atmel, ATTINY44A-PU Datasheet - Page 140
ATTINY44A-PU
Manufacturer Part Number
ATTINY44A-PU
Description
IC MCU AVR 4K FLASH 20MHZ 14PDIP
Manufacturer
Atmel
Series
AVR® ATtinyr
Specifications of ATTINY44A-PU
Core Processor
AVR
Core Size
8-Bit
Speed
20MHz
Connectivity
USI
Peripherals
Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
Number Of I /o
12
Program Memory Size
4KB (2K x 16)
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
256 x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
14-DIP (0.300", 7.62mm)
Processor Series
ATTINY4x
Core
AVR8
Data Bus Width
8 bit
Data Ram Size
256 B
Interface Type
SPI/USI
Maximum Clock Frequency
20 MHz
Number Of Programmable I/os
12
Number Of Timers
2
Maximum Operating Temperature
+ 85 C
Mounting Style
Through Hole
3rd Party Development Tools
EWAVR, EWAVR-BL
Development Tools By Supplier
ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT
Minimum Operating Temperature
- 40 C
On-chip Adc
20-ch x 10-bit
For Use With
ATSTK600 - DEV KIT FOR AVR/AVR32770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAGATAVRISP2 - PROGRAMMER AVR IN SYSTEM
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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16.9
16.10 ADC Accuracy Definitions
140
Noise Canceling Techniques
ATtiny24A/44A/84A
In order to avoid distortion from unpredictable signal convolution, signal components higher than
the Nyquist frequency (f
quency components with a low-pass filter before applying the signals as inputs to the ADC.
Figure 16-8.
Note:
Digital circuitry inside and outside the device generates EMI which might affect the accuracy of
analog measurements. When conversion accuracy is critical, the noise level can be reduced by
applying the following techniques:
Where high ADC accuracy is required it is recommended to use ADC Noise Reduction Mode, as
described in
is above 1 MHz, or when the ADC is used for reading the internal temperature sensor, as
described in
bypass capacitors does reduce the need for using ADC Noise Reduction Mode
An n-bit single-ended ADC converts a voltage linearly between GND and V
(LSBs). The lowest code is read as 0, and the highest code is read as 2
Several parameters describe the deviation from the ideal behavior, as follows:
• Keep analog signal paths as short as possible.
• Make sure analog tracks run over the analog ground plane.
• Keep analog tracks well away from high-speed switching digital tracks.
• If any port pin is used as a digital output, it mustn’t switch while a conversion is in progress.
• Place bypass capacitors as close to V
The capacitor in the figure depicts the total capacitance, including the sample/hold capacitor and
any stray or parasitic capacitance inside the device. The value given is worst case.
ADCn
Section 16.7 on page
Section 16.12 on page
Analog Input Circuitry
ADC
/2) should not be present. The user is advised to remove high fre-
I
IH
139. This is especially the case when system clock frequency
I
IL
143. A good system design with properly placed, external
CC
and GND pins as possible.
1..100 kohm
C
S/H
= 14 pF
n
-1.
V
CC
REF
/2
8183C–AVR–03/11
in 2
n
steps
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