PIC16LF627A-I/SO Microchip Technology, PIC16LF627A-I/SO Datasheet - Page 48
PIC16LF627A-I/SO
Manufacturer Part Number
PIC16LF627A-I/SO
Description
IC MCU FLASH 1KX14 EEPROM 18SOIC
Manufacturer
Microchip Technology
Series
PIC® 16Fr
Datasheets
1.PIC16F627A-IP.pdf
(180 pages)
2.PIC16LF627A-IP.pdf
(8 pages)
3.PIC16LF627A-ISO.pdf
(180 pages)
Specifications of PIC16LF627A-I/SO
Core Size
8-Bit
Program Memory Size
1.75KB (1K x 14)
Core Processor
PIC
Speed
20MHz
Connectivity
UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
16
Program Memory Type
FLASH
Eeprom Size
128 x 8
Ram Size
224 x 8
Voltage - Supply (vcc/vdd)
2 V ~ 5.5 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
18-SOIC (7.5mm Width)
Controller Family/series
PIC16LF
No. Of I/o's
16
Eeprom Memory Size
128Byte
Ram Memory Size
224Byte
Cpu Speed
20MHz
No. Of Timers
3
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Data Converters
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
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PIC16F627A/628A/648A
6.3
An 8-bit counter is available as a prescaler for the
Timer0 module, or as a postscaler for the Watchdog
Timer. A prescaler assignment for the Timer0 module
means that there is no postscaler for the Watchdog
Timer, and vice-versa.
FIGURE 6-1:
DS40044D-page 46
WDT Enable bit
T0CKI
Watchdog
pin
Timer
Timer0 Prescaler
Note:
F
OSC
/4
T0SE, T0CS, PSA, PS<2:0> are bits in the Option Register.
T0SE
BLOCK DIAGRAM OF THE TIMER0/WDT
TMR1 Clock Source
PSA
0
1
.
T0CS
0
1
WDT Postscaler/
TMR0 Prescaler
8-to-1MUX
8
PSA
PSA
1
0
1
0
The PSA and PS<2:0> bits (OPTION<3:0>) determine
the prescaler assignment and prescale ratio.
When assigned to the Timer0 module, all instructions
writing to the TMR0 register (e.g., CLRF 1, MOVWF 1,
BSF 1, x....etc.) will clear the prescaler. When
assigned to WDT, a CLRWDT instruction will clear the
prescaler along with the Watchdog Timer. The prescaler
is not readable or writable.
Time-out
WDT
Cycles
PS<2:0>
SYNC
2
© 2005 Microchip Technology Inc.
TMR0 Reg
Data Bus
8
Set flag bit T0IF
on Overflow
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