ATTINY2313-20MU Atmel, ATTINY2313-20MU Datasheet - Page 133
![IC MCU AVR 2K FLASH 20MLF](/photos/6/87/68751/313-20-qfn_sml.jpg)
ATTINY2313-20MU
Manufacturer Part Number
ATTINY2313-20MU
Description
IC MCU AVR 2K FLASH 20MLF
Manufacturer
Atmel
Series
AVR® ATtinyr
Specifications of ATTINY2313-20MU
Core Processor
AVR
Core Size
8-Bit
Speed
20MHz
Connectivity
SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
18
Program Memory Size
2KB (1K x 16)
Program Memory Type
FLASH
Eeprom Size
128 x 8
Ram Size
128 x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
20-MLF®, QFN
Processor Series
ATTINY2x
Core
AVR8
Data Bus Width
8 bit
Data Ram Size
128 B
Interface Type
SPI/UART/USI
Maximum Clock Frequency
20 MHz
Number Of Programmable I/os
18
Number Of Timers
2
Operating Supply Voltage
2.7 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWAVR, EWAVR-BL
Development Tools By Supplier
ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT
Minimum Operating Temperature
- 40 C
Package
20MLF EP
Device Core
AVR
Family Name
ATtiny
Maximum Speed
20 MHz
For Use With
ATSTK600-DIP40 - STK600 SOCKET/ADAPTER 40-PDIP770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAGATAVRDRAGON - KIT DRAGON 32KB FLASH MEM AVRATAVRISP2 - PROGRAMMER AVR IN SYSTEMATJTAGICE2 - AVR ON-CHIP D-BUG SYSTEM
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Data Converters
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
Q2312268A
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ATTINY2313-20MU
Manufacturer:
原装ATMEL
Quantity:
20 000
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- Download datasheet (4Mb)
USART Baud Rate
Registers – UBRRL
and UBRRH
2543L–AVR–08/10
Table 54. UCSZ Bits Settings
• Bit 0 – UCPOL: Clock Polarity
This bit is used for synchronous mode only. Write this bit to zero when asynchronous mode is
used. The UCPOL bit sets the relationship between data output change and data input sample,
and the synchronous clock (XCK).
Table 55. UCPOL Bit Settings
• Bit 15:12 – Reserved Bits
These bits are reserved for future use. For compatibility with future devices, these bit must be
written to zero when UBRRH is written.
• Bit 11:0 – UBRR11:0: USART Baud Rate Register
This is a 12-bit register which contains the USART baud rate. The UBRRH contains the four
most significant bits, and the UBRRL contains the eight least significant bits of the USART baud
rate. Ongoing transmissions by the Transmitter and Receiver will be corrupted if the baud rate is
changed. Writing UBRRL will trigger an immediate update of the baud rate prescaler.
Bit
Read/Write
Initial Value
UCPOL
0
1
UCSZ2
0
0
0
0
1
1
1
1
Transmitted Data Changed (Output of
TxD Pin)
Rising XCK Edge
Falling XCK Edge
R/W
15
R
–
7
0
0
R/W
14
UCSZ1
R
–
6
0
0
0
0
1
1
0
0
1
1
R/W
13
R
–
5
0
0
R/W
12
R
–
4
0
0
UBRR[7:0]
UCSZ0
0
1
0
1
0
1
0
1
R/W
R/W
11
3
0
0
Received Data Sampled (Input on
RxD Pin)
Falling XCK Edge
Rising XCK Edge
R/W
R/W
Character Size
5-bit
6-bit
7-bit
8-bit
Reserved
Reserved
Reserved
9-bit
10
2
0
0
UBRR[11:8]
R/W
R/W
9
1
0
0
R/W
R/W
8
0
0
0
UBRRH
UBRRL
133
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