ATTINY2313-20MU Atmel, ATTINY2313-20MU Datasheet - Page 49
![IC MCU AVR 2K FLASH 20MLF](/photos/6/87/68751/313-20-qfn_sml.jpg)
ATTINY2313-20MU
Manufacturer Part Number
ATTINY2313-20MU
Description
IC MCU AVR 2K FLASH 20MLF
Manufacturer
Atmel
Series
AVR® ATtinyr
Specifications of ATTINY2313-20MU
Core Processor
AVR
Core Size
8-Bit
Speed
20MHz
Connectivity
SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
18
Program Memory Size
2KB (1K x 16)
Program Memory Type
FLASH
Eeprom Size
128 x 8
Ram Size
128 x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
20-MLF®, QFN
Processor Series
ATTINY2x
Core
AVR8
Data Bus Width
8 bit
Data Ram Size
128 B
Interface Type
SPI/UART/USI
Maximum Clock Frequency
20 MHz
Number Of Programmable I/os
18
Number Of Timers
2
Operating Supply Voltage
2.7 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWAVR, EWAVR-BL
Development Tools By Supplier
ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT
Minimum Operating Temperature
- 40 C
Package
20MLF EP
Device Core
AVR
Family Name
ATtiny
Maximum Speed
20 MHz
For Use With
ATSTK600-DIP40 - STK600 SOCKET/ADAPTER 40-PDIP770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAGATAVRDRAGON - KIT DRAGON 32KB FLASH MEM AVRATAVRISP2 - PROGRAMMER AVR IN SYSTEMATJTAGICE2 - AVR ON-CHIP D-BUG SYSTEM
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Data Converters
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
Q2312268A
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ATTINY2313-20MU
Manufacturer:
原装ATMEL
Quantity:
20 000
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- Download datasheet (4Mb)
2543L–AVR–08/10
Consider the clock period starting shortly after the first falling edge of the system clock. The latch
is closed when the clock is low, and goes transparent when the clock is high, as indicated by the
shaded region of the “SYNC LATCH” signal. The signal value is latched when the system clock
goes low. It is clocked into the PINxn Register at the succeeding positive clock edge. As indi-
cated by the two arrows tpd,max and tpd,min, a single signal transition on the pin will be delayed
between ½ and 1½ system clock period depending upon the time of assertion.
When reading back a software assigned pin value, a nop instruction must be inserted as indi-
cated in
clock. In this case, the delay tpd through the synchronizer is 1 system clock period.
Figure 24. Synchronization when Reading a Software Assigned Pin Value
INSTRUCTIONS
Figure
SYSTEM CLK
SYNC LATCH
24. The out instruction sets the “SYNC LATCH” signal at the positive edge of the
PINxn
r16
r17
out PORTx, r16
0x00
nop
t
pd
0xFF
in r17, PINx
0xFF
49
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