PIC16F724-I/ML Microchip Technology, PIC16F724-I/ML Datasheet - Page 156

IC PIC MCU FLASH 4KX14 44-QFN

PIC16F724-I/ML

Manufacturer Part Number
PIC16F724-I/ML
Description
IC PIC MCU FLASH 4KX14 44-QFN
Manufacturer
Microchip Technology
Series
PIC® XLP™ 16Fr

Specifications of PIC16F724-I/ML

Core Size
8-Bit
Program Memory Size
7KB (4K x 14)
Oscillator Type
Internal
Core Processor
PIC
Speed
20MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
36
Program Memory Type
FLASH
Ram Size
192 x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 14x8b
Operating Temperature
-40°C ~ 85°C
Package / Case
44-QFN
Controller Family/series
PIC16F
No. Of I/o's
36
Ram Memory Size
192Byte
Cpu Speed
20MHz
No. Of Timers
3
No. Of Pwm
RoHS Compliant
Processor Series
PIC16F
Core
PIC
Data Bus Width
8 bit
Data Ram Size
192 B
Interface Type
I2C, SCI, SPI
Maximum Clock Frequency
20 MHz
Number Of Programmable I/os
36
Number Of Timers
3
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120
Minimum Operating Temperature
- 40 C
On-chip Adc
8 bit, 14 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
AC164112 - VOLTAGE LIMITER MPLAB ICD2 VPPAC164322 - MODULE SOCKET MPLAB PM3 28/44QFN444-1001 - DEMO BOARD FOR PICMICRO MCU
Eeprom Size
-
Lead Free Status / Rohs Status
 Details
PIC16F72X/PIC16LF72X
16.2
The Baud Rate Generator (BRG) is an 8-bit timer that
is dedicated to the support of both the asynchronous
and synchronous AUSART operation.
The SPBRG register determines the period of the free
running baud rate timer. In Asynchronous mode the
multiplier of the baud rate period is determined by the
BRGH bit of the TXSTA register. In Synchronous mode,
the BRGH bit is ignored.
Table 16-3 contains the formulas for determining the
baud rate. Example 16-1 provides a sample calculation
for determining the baud rate and baud rate error.
Typical baud rates and error values for various
asynchronous modes have been computed for your
convenience and are shown in Table 16-3. It may be
advantageous to use the high baud rate (BRGH = 1), to
reduce the baud rate error.
Writing a new value to the SPBRG register causes the
BRG timer to be reset (or cleared). This ensures that
the BRG does not wait for a timer overflow before
outputting the new baud rate.
TABLE 16-3:
TABLE 16-4:
DS41341E-page 156
Legend:
RCSTA
SPBRG
TXSTA
Legend:
Name
SYNC
0
0
1
AUSART Baud Rate Generator
(BRG)
Configuration Bits
x = Don’t care, n = value of SPBRG register
x = unknown, - = unimplemented read as ‘0’. Shaded cells are not used for the Baud Rate Generator.
SPEN
BRG7
CSRC
Bit 7
BAUD RATE FORMULAS
REGISTERS ASSOCIATED WITH THE BAUD RATE GENERATOR
BRG6
Bit 6
BRGH
RX9
TX9
0
1
x
SREN
BRG5
TXEN
Bit 5
CREN
BRG4
SYNC
Bit 4
AUSART Mode
Asynchronous
Asynchronous
Synchronous
ADDEN
BRG3
Bit 3
BRG2
BRGH
FERR
EXAMPLE 16-1:
Bit 2
For a device with F
9600, and Asynchronous mode with SYNC = 0 and BRGH
= 0 (as seen in Table 16-3):
Solving for SPBRG:
%
Desired Baud Rate
Error
Actual Baud Rate
OERR
TRMT
BRG1
Bit 1
=
=
SPBRG
Actual Baud Rate Desired Baud Rate
------------------------------------------------------------------------------------------------- -
9615 9600
----------------------------- -
9600
OSC
RX9D
BRG0
TX9D
Bit 0
=
=
=
=
=
=
CALCULATING BAUD
RATE ERROR
Desired Baud Rate
[
-------------------------- -
64 25
9615
of 16 MHz, desired baud rate of
-------------------------------------- -
64 SPBRG
© 2009 Microchip Technology Inc.
16000000
25.042
-------------------------------------------------------- -
64 Desired Baud Rate
16000000
----------------------- -
64
Baud Rate Formula
(
(
100
(
(
F
F
F
9600
F
OSC
OSC
0000 000x
0000 0000
0000 -010
OSC
POR, BOR
+
OS C
Value on
]
=
1
=
/[64 (n+1)]
/[16 (n+1)]
F
)
)
/[4 (n+1)]
0.16%
OS C
+
25
1
1
)
0000 000x
0000 0000
0000 -010
)
Value on
all other
Resets
1
100

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