PIC18LF14K50-I/SS Microchip Technology, PIC18LF14K50-I/SS Datasheet - Page 163

• Manufacturer Part Number: PIC18LF14K50-I/SS
• Description: IC PIC MCU FLASH 16K 1.8V 20SSOP
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 18Fr

Specifications of PIC18LF14K50-I/SS

• Core Size: 8-Bit
• Program Memory Size: 16KB (8K x 16)
• Core Processor: PIC
• Speed: 48MHz
• Connectivity: I²C, SPI, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 14
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 768 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 11x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 20-SSOP
• Controller Family/series: PIC18
• No. Of I/o's: 15
• Eeprom Memory Size: 256Byte
• Ram Memory Size: 768Byte
• Cpu Speed: 48MHz
• No. Of Timers: 4
• Processor Series: PIC18LF
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 256 B
• Interface Type: EUSART, I2C, MSSP, SPI, USB
• Maximum Clock Frequency: 32 KHz
• Number Of Programmable I/os: 18
• Number Of Timers: 4
• Operating Supply Voltage: 1.8 V to 3.6 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, DM164127, DV164126
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 12 Channel
• Package: 20SSOP
• Device Core: PIC
• Family Name: PIC18
• Maximum Speed: 48 MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

15.3.6
Master mode is enabled by setting and clearing the
appropriate SSPM bits in SSPCON1 and by setting the
SSPEN bit. In Master mode, the SCL and SDA lines
are manipulated by the MSSP hardware.
Master mode of operation is supported by interrupt
generation on the detection of the Start and Stop con-
ditions. The Stop (P) and Start (S) bits are cleared from
a Reset or when the MSSP module is disabled. Control
of the I
bus is Idle, with both the S and P bits clear.
In Firmware Controlled Master mode, user code
conducts all I
Stop bit conditions.
Once Master mode is enabled, the user has six
options.
1.
2.
3.
4.
5.
6.
FIGURE 15-16:
© 2009 Microchip Technology Inc.
Assert a Start condition on SDA and SCL.
Assert a Repeated Start condition on SDA and
SCL.
Write
transmission of data/address.
Configure the I
Generate an Acknowledge condition at the end
of a received byte of data.
Generate a Stop condition on SDA and SCL.
SDA
SCL
2
C bus may be taken when the P bit is set, or the
MASTER MODE
to
2
C bus operations based on Start and
the
2
C port to receive data.
SSPBUF
MSSP BLOCK DIAGRAM (I
SDA In
Bus Collision
SCL In
register
Read
PIC18F1XK50/PIC18LF1XK50
initiating
MSb
Write Collision Detect
Start bit, Stop bit,
end of XMIT/RCV
State Counter for
Clock Arbitration
Acknowledge
Start bit Detect
Stop bit Detect
SSPBUF
Generate
SSPSR
Preliminary
2
C™ MASTER MODE)
LSb
Write
The following events will cause the SSP Interrupt Flag
bit, SSPIF, to be set (SSP interrupt, if enabled):
• Start condition
• Stop condition
• Data transfer byte transmitted/received
• Acknowledge transmit
• Repeated Start
Clock
Data Bus
Shift
Note:
Internal
Set/Reset, S, P, WCOL
Set SSPIF, BCLIF
Reset ACKSTAT, PEN
The MSSP module, when configured in
I
of events. For instance, the user is not
allowed to initiate a Start condition and
immediately write the SSPBUF register to
initiate transmission before the Start
condition is complete. In this case, the
SSPBUF will not be written to and the
WCOL bit will be set, indicating that a write
to the SSPBUF did not occur.
2
C Master mode, does not allow queueing
SSPM<3:0>
SSPADD<6:0>
Generator
Baud
Rate
DS41350C-page 161