PIC18LF13K50-I/P Microchip Technology, PIC18LF13K50-I/P Datasheet - Page 151
![IC PIC MCU FLASH 4KX16 20-PDIP](/photos/12/13/121303/150-20-dip_sml.jpg)
PIC18LF13K50-I/P
Manufacturer Part Number
PIC18LF13K50-I/P
Description
IC PIC MCU FLASH 4KX16 20-PDIP
Manufacturer
Microchip Technology
Series
PIC® XLP™ 18Fr
Datasheets
1.PIC18F13K50-ISS.pdf
(420 pages)
2.PIC18F13K50-ISS.pdf
(40 pages)
3.PIC18F13K50-ISS.pdf
(10 pages)
4.PIC18F13K50-ISS.pdf
(2 pages)
5.PIC18F13K50-ISO.pdf
(414 pages)
Specifications of PIC18LF13K50-I/P
Core Size
8-Bit
Program Memory Size
8KB (4K x 16)
Core Processor
PIC
Speed
48MHz
Connectivity
I²C, SPI, UART/USART, USB
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
14
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 3.6 V
Data Converters
A/D 11x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
20-DIP (0.300", 7.62mm)
Controller Family/series
PIC18
No. Of I/o's
15
Eeprom Memory Size
256Byte
Ram Memory Size
512Byte
Cpu Speed
48MHz
No. Of Timers
4
Processor Series
PIC18LF
Core
PIC
Data Bus Width
8 bit
Data Ram Size
256 B
Interface Type
EUSART, I2C, MSSP, SPI, USB
Maximum Clock Frequency
32 KHz
Number Of Programmable I/os
18
Number Of Timers
4
Operating Supply Voltage
1.8 V to 3.6 V
Maximum Operating Temperature
+ 125 C
Mounting Style
Through Hole
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, DM164127, DV164126
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 12 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
- PIC18F13K50-ISS PDF datasheet
- PIC18F13K50-ISS PDF datasheet #2
- PIC18F13K50-ISS PDF datasheet #3
- PIC18F13K50-ISS PDF datasheet #4
- PIC18F13K50-ISO PDF datasheet #5
- Current page: 151 of 420
- Download datasheet (4Mb)
REGISTER 15-5:
2010 Microchip Technology Inc.
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Note 1:
R/W-0
GCEN
2:
For bits ACKEN, RCEN, PEN, RSEN, SEN: If the I
be set (no spooling) and the SSPBUF may not be written (or writes to the SSPBUF are disabled).
Value that will be transmitted when the user initiates an Acknowledge sequence at the end of a receive.
GCEN: General Call Enable bit (Slave mode only)
1 = Generate interrupt when a general call address 0x00 or 00h is received in the SSPSR
0 = General call address disabled
ACKSTAT: Acknowledge Status bit (Master Transmit mode only)
1 = Acknowledge was not received from slave
0 = Acknowledge was received from slave
ACKDT: Acknowledge Data bit (Master Receive mode only)
1 = Not Acknowledge
0 = Acknowledge
ACKEN: Acknowledge Sequence Enable bit (Master Receive mode only)
1 = Initiate Acknowledge sequence on SDA and SCL pins and transmit ACKDT data bit.
0 = Acknowledge sequence Idle
RCEN: Receive Enable bit (Master mode only)
1 = Enables Receive mode for I
0 = Receive Idle
PEN: Stop Condition Enable bit (Master mode only)
1 = Initiate Stop condition on SDA and SCL pins. Automatically cleared by hardware.
0 = Stop condition Idle
RSEN: Repeated Start Condition Enable bit (Master mode only)
1 = Initiate Repeated Start condition on SDA and SCL pins. Automatically cleared by hardware.
0 = Repeated Start condition Idle
SEN: Start Condition Enable/Stretch Enable bit
In Master mode:
1 = Initiate Start condition on SDA and SCL pins. Automatically cleared by hardware.
0 = Start condition Idle
In Slave mode:
1 = Clock stretching is enabled for both slave transmit and slave receive (stretch enabled)
0 = Clock stretching is disabled
ACKSTAT
R/W-0
Automatically cleared by hardware.
SSPCON2: MSSP CONTROL REGISTER (I
W = Writable bit
‘1’ = Bit is set
ACKDT
R/W-0
(2)
ACKEN
2
R/W-0
C
Preliminary
(1)
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
RCEN
2
(1)
C module is not in the Idle mode, these bits may not
R/W-0
(1)
(1)
(1)
2
C MODE)
PIC18F/LF1XK50
(2)
PEN
R/W-0
(1)
(1)
x = Bit is unknown
(1)
RSEN
R/W-0
(1)
DS41350E-page 151
SEN
R/W-0
(1)
bit 0
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