PIC18LF13K50-I/P Microchip Technology, PIC18LF13K50-I/P Datasheet - Page 57
![IC PIC MCU FLASH 4KX16 20-PDIP](/photos/12/13/121303/150-20-dip_sml.jpg)
PIC18LF13K50-I/P
Manufacturer Part Number
PIC18LF13K50-I/P
Description
IC PIC MCU FLASH 4KX16 20-PDIP
Manufacturer
Microchip Technology
Series
PIC® XLP™ 18Fr
Datasheets
1.PIC18F13K50-ISS.pdf
(420 pages)
2.PIC18F13K50-ISS.pdf
(40 pages)
3.PIC18F13K50-ISS.pdf
(10 pages)
4.PIC18F13K50-ISS.pdf
(2 pages)
5.PIC18F13K50-ISO.pdf
(414 pages)
Specifications of PIC18LF13K50-I/P
Core Size
8-Bit
Program Memory Size
8KB (4K x 16)
Core Processor
PIC
Speed
48MHz
Connectivity
I²C, SPI, UART/USART, USB
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
14
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 3.6 V
Data Converters
A/D 11x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
20-DIP (0.300", 7.62mm)
Controller Family/series
PIC18
No. Of I/o's
15
Eeprom Memory Size
256Byte
Ram Memory Size
512Byte
Cpu Speed
48MHz
No. Of Timers
4
Processor Series
PIC18LF
Core
PIC
Data Bus Width
8 bit
Data Ram Size
256 B
Interface Type
EUSART, I2C, MSSP, SPI, USB
Maximum Clock Frequency
32 KHz
Number Of Programmable I/os
18
Number Of Timers
4
Operating Supply Voltage
1.8 V to 3.6 V
Maximum Operating Temperature
+ 125 C
Mounting Style
Through Hole
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, DM164127, DV164126
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 12 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
- PIC18F13K50-ISS PDF datasheet
- PIC18F13K50-ISS PDF datasheet #2
- PIC18F13K50-ISS PDF datasheet #3
- PIC18F13K50-ISS PDF datasheet #4
- PIC18F13K50-ISO PDF datasheet #5
- Current page: 57 of 420
- Download datasheet (4Mb)
4.5
The programming block size is 8 or 16 bytes,
depending on the device (See
programming is not supported.
Table writes are used internally to load the holding
registers needed to program the Flash memory. There
are only as many holding registers as there are bytes
in a write block (See
Since the Table Latch (TABLAT) is only a single byte,
the TBLWT instruction may need to be executed 8, or 16
times, depending on the device, for each programming
operation. All of the table write operations will essen-
tially be short writes because only the holding registers
are written. After all the holding registers have been
written, the programming operation of that block of
memory is started by configuring the EECON1 register
for a program memory write and performing the long
write sequence.
FIGURE 4-5:
4.5.1
The sequence of events for programming an internal
program memory location should be:
1.
2.
3.
4.
5.
6.
7.
2010 Microchip Technology Inc.
TBLPTR = xxxx00
Read 64 bytes into RAM.
Update data values in RAM as necessary.
Load Table Pointer register with address being
erased.
Execute the block erase procedure.
Load Table Pointer register with address of first
byte being written.
Write the 8 or 16-byte block into the holding
registers with auto-increment.
Set the EECON1 register for the write operation:
• set EEPGD bit to point to program memory;
• clear the CFGS bit to access program memory;
• set WREN to enable byte writes.
Note 1: YY = x7, xF, or 1F for 8, 16 or 32 byte write blocks, respectively.
Writing to Flash Program Memory
FLASH PROGRAM MEMORY WRITE
SEQUENCE
Holding Register
Table
8
TABLE WRITES TO FLASH PROGRAM MEMORY
4-1).
TBLPTR = xxxx01
Table
4-1). Word or byte
Holding Register
PIC18F1XK50/PIC18LF1XK50
8
Preliminary
Program Memory
TBLPTR = xxxx02
Write Register
TABLAT
The long write is necessary for programming the inter-
nal Flash. Instruction execution is halted during a long
write cycle. The long write will be terminated by the
internal programming timer.
The EEPROM on-chip timer controls the write time.
The write/erase voltages are generated by an on-chip
charge pump, rated to operate over the voltage range
of the device.
8.
9.
10. Write 0AAh to EECON2.
11. Set the WR bit. This will begin the write cycle.
12. The CPU will stall for duration of the write (about
13. Re-enable interrupts.
14. Repeat steps 6 to 13 for each block until all 64
15. Verify the memory (table read).
This procedure will require about 6 ms to update each
write block of memory. An example of the required code
is given in
Holding Register
Note:
Note:
Disable interrupts.
Write 55h to EECON2.
2 ms using internal timer).
bytes are written.
Example
8
The default value of the holding registers on
device Resets and after write operations is
FFh. A write of FFh to a holding register
does not modify that byte. This means that
individual bytes of program memory may
be modified, provided that the change does
not attempt to change any bit from a ‘0’ to a
‘1’. When modifying individual bytes, it is
not necessary to load all holding registers
before executing a long write operation.
Before setting the WR bit, the Table
Pointer address needs to be within the
intended address range of the bytes in the
holding registers.
4-3.
TBLPTR = xxxxYY
Holding Register
DS41350E-page 57
(1)
8
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