PIC16F707-I/ML Microchip Technology, PIC16F707-I/ML Datasheet - Page 168

• Manufacturer Part Number: PIC16F707-I/ML
• Description: IC MCU 8BIT FLASH 44QFN
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 16Fr

Specifications of PIC16F707-I/ML

• Core Size: 8-Bit
• Program Memory Size: 14KB (8K x 14)
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Core Processor: PIC
• Speed: 20MHz
• Connectivity: I²C, SPI, UART/USART
• Number Of I /o: 36
• Program Memory Type: FLASH
• Ram Size: 363 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 14x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-QFN
• Controller Family/series: PIC16F
• No. Of I/o's: 36
• Ram Memory Size: 363Byte
• Cpu Speed: 20MHz
• No. Of Timers: 6
• Processor Series: PIC16F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 368 B
• Interface Type: I2C, SPI, AUSART
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 36
• Number Of Timers: 4
• Operating Supply Voltage: 1.8 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8 bit, 14 Channel
• On-chip Dac: 5 bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

PIC16F707/PIC16LF707
19.2.2
During times of no data transfer (Idle time), both the
clock line (SCL) and the data line (SDA) are pulled high
through external pull-up resistors. The Start and Stop
conditions determine the start and stop of data trans-
mission. The Start condition is defined as a high-to-low
transition of the SDA line while SCL is high. The Stop
condition is defined as a low-to-high transition of the
SDA line while SCL is high.
FIGURE 19-9:
19.2.3
After the valid reception of an address or data byte, the
hardware automatically will generate the Acknowledge
(ACK) pulse and load the SSPBUF register with the
received value currently in the SSPSR register. There
are certain conditions that will cause the SSP module
not to generate this ACK pulse. They include any or all
of the following:
• The Buffer Full bit, BF of the SSPSTAT register,
• The SSP Overflow bit, SSPOV of the SSPCON
• The SSP Module is being operated in Firmware
TABLE 19-2:
DS41418A-page 168
was set before the transfer was received.
register, was set before the transfer was received.
Master mode.
Note:
Transfer is Received
Status Bits as Data
BF
0
1
1
0
SDA
SCL
START AND STOP CONDITIONS
ACKNOWLEDGE
Shaded cells show the conditions where the user software did not properly clear the overflow condition.
SSPOV
DATA TRANSFER RECEIVED BYTE ACTIONS
0
0
1
1
START AND STOP CONDITIONS
Condition
Start
S
SSPSR  SSPBUF
Data Allowed
Change of
Yes
No
No
No
Preliminary
Figure 19-9 shows the Start and Stop conditions. A
master device generates these conditions for starting
and terminating data transfer. Due to the definition of
the Start and Stop conditions, when data is being trans-
mitted, the SDA line can only change state when the
SCL line is low.
In such a case, the SSPSR register value is not loaded
into the SSPBUF, but bit SSPIF of the PIR1 register is
set. Table 19-2 shows the results of when a data
transfer byte is received, given the status of bits BF and
SSPOV. Flag bit BF is cleared by reading the SSPBUF
register, while bit SSPOV is cleared through software.
Generate ACK
Pulse
Yes
No
No
No
Data Allowed
Change of
 2010 Microchip Technology Inc.
(SSP Interrupt occurs
Condition
Stop
Set bit SSPIF
P
if enabled)
Yes
Yes
Yes
Yes