PIC16LF72-I/SP Microchip Technology, PIC16LF72-I/SP Datasheet

IC PIC MCU FLASH 2KX14 28DIP

PIC16LF72-I/SP

Manufacturer Part Number
PIC16LF72-I/SP
Description
IC PIC MCU FLASH 2KX14 28DIP
Manufacturer
Microchip Technology
Series
PIC® 16Fr

Specifications of PIC16LF72-I/SP

Core Size
8-Bit
Program Memory Size
3.5KB (2K x 14)
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Core Processor
PIC
Speed
20MHz
Connectivity
I²C, SPI
Number Of I /o
22
Program Memory Type
FLASH
Ram Size
128 x 8
Voltage - Supply (vcc/vdd)
2 V ~ 5.5 V
Data Converters
A/D 5x8b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
28-DIP (0.300", 7.62mm)
Controller Family/series
PIC16LF
No. Of I/o's
22
Ram Memory Size
128Byte
Cpu Speed
16MHz
No. Of Timers
3
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
PIC16LF72-I/SP
Manufacturer:
MICROCHIP
Quantity:
6 000
M
PIC16F72
Data Sheet
28-Pin, 8-Bit CMOS FLASH
Microcontroller with A/D Converter
 2002 Microchip Technology Inc.
DS39597B

Related parts for PIC16LF72-I/SP

PIC16LF72-I/SP Summary of contents

Page 1

... Microcontroller with A/D Converter  2002 Microchip Technology Inc. M Data Sheet 28-Pin, 8-Bit CMOS FLASH PIC16F72 DS39597B ...

Page 2

... Serialized Quick Turn Programming (SQTP service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. © 2002, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Printed on recycled paper. Microchip received QS-9000 quality system ...

Page 3

... Wide operating voltage range: 2.0V to 5.5V • Industrial temperature range • Low power consumption: - < 0.6 mA typical @ 3V, 4 MHz - 20 µA typical @ 3V, 32 kHz - < 1 µA typical standby current  2002 Microchip Technology Inc. PIC16F72 Pin Diagrams PDIP, SOIC, SSOP MCLR/V • 1 ...

Page 4

... Data Memory - RAM (8-bit bytes) Interrupts I/O Ports Timers Capture/Compare/PWM Modules Serial Communications 8-bit A/D Converter Instruction Set (No. of Instructions) DS39597B-page 2 PIC16F72 MHz POR, BOR, (PWRT, OST) 2K 128 8 PORTA, PORTB, PORTC Timer0, Timer1, Timer2 1 SSP 5 channels 35  2002 Microchip Technology Inc. ...

Page 5

... When contacting a sales office or the literature center, please specify which device, revision of silicon and data sheet (include literature number) you are using. Customer Notification System Register on our web site at www.microchip.com/cn to receive the most current information on all of our products.  2002 Microchip Technology Inc. PIC16F72 DS39597B-page 3 ...

Page 6

... PIC16F72 NOTES: DS39597B-page 4  2002 Microchip Technology Inc. ...

Page 7

... Synchronous A/D Serial Port Note 1: Higher order bits are from the STATUS register.  2002 Microchip Technology Inc. The program memory contains 2K words, which trans- late to 2048 instructions, since each 14-bit program memory word is the same width as each device instruction. The data memory (RAM) contains 128 bytes. ...

Page 8

... RC4 can also be the SPI Data In (SPI mode Data I mode). ST RC5 can also be the SPI Data Out (SPI mode — Ground reference for logic and I/O pins. — Positive supply for logic and I/O pins. I/O = input/output P = power ST = Schmitt Trigger input Description  2002 Microchip Technology Inc. ...

Page 9

... Stack Level 8 RESET Vector Interrupt Vector On-chip Program Memory  2002 Microchip Technology Inc. 2.2 Data Memory Organization The Data Memory is partitioned into multiple banks that contain the General Purpose Registers and the Special Function Registers. Bits RP1 (STATUS<6>) and RP0 (STATUS< ...

Page 10

... PCLATH 18Ah 10Bh INTCON 18Bh 10Ch PMCON1 18Ch 10Dh 18Dh 10Eh 18Eh 10Fh 18Fh 110h 190h 11Fh 19Fh 1A0h 120h accesses A0h -BFh 1BFh 1C0h accesses 40h -7Fh 17Fh 1FFh Bank 3  2002 Microchip Technology Inc. ...

Page 11

... The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<12:8> whose contents are transferred to the upper byte of the program counter. 3: This bit always reads as a ‘1’.  2002 Microchip Technology Inc. The Special Function Registers can be classified into two sets: core (CPU) and peripheral. Those registers associated with the core functions are described in detail in this section ...

Page 12

... 0000 0000 — — — — — — — — — — — — — — — — — — — — PCFG1 PCFG0 54 ---- -000  2002 Microchip Technology Inc. ...

Page 13

... The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<12:8> whose contents are transferred to the upper byte of the program counter. 3: This bit always reads as a ‘1’.  2002 Microchip Technology Inc. Bit 5 Bit 4 Bit 3 ...

Page 14

... See the SUBLW and SUBWF instructions for examples. R/W-0 R-1 R-1 R/W-x RP0 Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared  2002 Microchip Technology Inc. R/W-x R/W bit 0 (1) (1, Bit is unknown ...

Page 15

... Bit Value TMR0 Rate WDT Rate 000 001 010 011 100 101 110 111 Legend Readable bit - n = Value at POR  2002 Microchip Technology Inc. Note: To achieve a 1:1 prescaler assignment for the TMR0 register, assign the prescaler to the Watchdog Timer. R/W-1 R/W-1 R/W-1 T0CS T0SE PSA ...

Page 16

... R/W-0 R/W-0 R/W-0 R/W-0 TMR0IE INTE RBIE TMR0IF W = Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared R/W-0 R/W-x INTF RBIF bit Bit is unknown  2002 Microchip Technology Inc. ...

Page 17

... Disables the TMR2 to PR2 match interrupt bit 0 TMR1IE: TMR1 Overflow Interrupt Enable bit 1 = Enables the TMR1 overflow interrupt 0 = Disables the TMR1 overflow interrupt Legend Readable bit - n = Value at POR  2002 Microchip Technology Inc. U-0 U-0 R/W-0 R/W-0 — — SSPIE CCP1IE W = Writable bit U = Unimplemented bit, read as ‘ ...

Page 18

... Legend Readable bit - n = Value at POR DS39597B-page 16 U-0 U-0 R/W-0 R/W-0 — — SSPIF CCP1IF W = Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared  2002 Microchip Technology Inc. R/W-0 R/W-0 TMR2IF TMR1IF bit Bit is unknown ...

Page 19

... No Brown-out Reset occurred Brown-out Reset occurred (must be set in software after a Brown-out Reset occurs) Legend Readable bit - n = Value at POR  2002 Microchip Technology Inc. Note: BOR is unknown on Power-on Reset. It must then be set by the user and checked on subsequent RESETS to see if BOR is clear, indicating a brown-out has occurred. ...

Page 20

... Top-of-Stack. PCL ALU result PCL Opcode <10:0> 13 PCL 0 11 Opcode <10:0> 13 PCL 0 11 Opcode <10:0> Stack (13-bits x 8) Top-of-Stack Stack (13-bits x 8) Top-of-Stack Stack (13-bits x 8) Top-of-Stack Stack (13-bits x 8) Top-of-Stack  2002 Microchip Technology Inc. ...

Page 21

... PUSH or POP. These are actions that occur from the execution of the CALL, RETURN, RETLW and RETFIE instructions, or the vectoring to an interrupt address.  2002 Microchip Technology Inc. PIC16F72 2.4 Program Memory Paging The CALL and GOTO instructions provide 11 bits of address to allow branching within any 2K program memory page ...

Page 22

... Bank Select Location Select 00h Data (1) Memory 7Fh Bank 0 Note 1: For register file map detail, see Figure 2-2. DS39597B-page 20 0 IRP Bank Select 80h 100h 180h FFh 17Fh 1FFh Bank 1 Bank 2 Bank 3 Indirect Addressing 7 0 FSR Register Location Select  2002 Microchip Technology Inc. ...

Page 23

... MOVWF ADCON1 ; as digital inputs MOVLW 0xCF ; Value used to ; initialize data ; direction MOVWF TRISA ; Set RA<3:0> as inputs ; RA<5:4> as outputs ; TRISA<7:6> are always ; read as ‘0’.  2002 Microchip Technology Inc. PIC16F72 FIGURE 3-1: BLOCK DIAGRAM OF RA3:RA0 AND RA5 PINS Data Bus Port ...

Page 24

... Input/output or analog input or slave select input for synchronous serial port. Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 RA5 RA4 RA3 RA2 RA1 — — — PCFG2 PCFG1 PCFG0 ---- -000 ---- -000 Value on Value on Bit 0 all other POR, BOR RESETS RA0 --0x 0000 --0u 0000 --11 1111 --11 1111  2002 Microchip Technology Inc. ...

Page 25

... RB7:RB4 pin configured as an output is excluded from the interrupt on change comparison). The input pins (of RB7:RB4)  2002 Microchip Technology Inc. are compared with the old value latched on the last read of PORTB. The “mismatch” outputs of RB7:RB4 are OR’ ...

Page 26

... Serial programming data. Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 RB5 RB4 RB3 RB2 RB1 PS2 PS1 Value on Value on all other POR, BOR RESETS RB0 xxxx xxxx uuuu uuuu 1111 1111 1111 1111 PS0 1111 1111 1111 1111  2002 Microchip Technology Inc. ...

Page 27

... Select Bank for TRISC MOVLW 0xCF ; Value used to ; initialize data ; direction MOVWF TRISC ; Set RC<3:0> as inputs ; RC<5:4> as outputs ; RC<7:6> as inputs  2002 Microchip Technology Inc. PIC16F72 FIGURE 3-5: PORTC BLOCK DIAGRAM (PERIPHERAL OUTPUT OVERRIDE) (1) Port/Peripheral Select Peripheral Data Out 0 Data Bus ...

Page 28

... Input/output port pin or Synchronous Serial Port data output. Input/output port pin. Input/output port pin. Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 RC5 RC4 RC3 RC2 RC1 mode). Value on Value on Bit 0 all other POR, BOR RESETS RC0 xxxx xxxx uuuu uuuu 1111 1111 1111 1111  2002 Microchip Technology Inc. ...

Page 29

... Does not initiate a FLASH read Legend Writable bit R = Readable bit ‘1’ = Bit is set  2002 Microchip Technology Inc. 4.1 PMADR The address registers can address maximum of 8K words of program FLASH. When selecting a program address value, the MSByte of the address is written to the PMADRH register and the LSByte is written to the PMADRL register ...

Page 30

... Data Register High Byte — — — — Value on Value on Bit 1 Bit 0 all other POR, BOR RESETS xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu — RD 1--- ---0 1--- ---0  2002 Microchip Technology Inc. ...

Page 31

... Timer PSA WDT Enable bit Note: T0CS, T0SE, PSA, PS2:PS0 are (OPTION<5:0>).  2002 Microchip Technology Inc. Counter mode is selected by setting bit T0CS (OPTION<5>). In Counter mode, Timer0 will incre- ment, either on every rising or falling edge of pin RA4/ T0CKI. The incrementing edge is determined by the Timer0 Source Edge Select bit T0SE (OPTION< ...

Page 32

... Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 TMR0IE INTE RBIE TMR0IF INTF T0SE PSA PS2 PS1 Value on Value on Bit 0 all other POR, BOR RESETS xxxx xxxx uuuu uuuu RBIF 0000 000x 0000 000u PS0 1111 1111 1111 1111  2002 Microchip Technology Inc. ...

Page 33

... TMR1ON: Timer1 On bit 1 = Enables Timer1 0 = Stops Timer1 Legend Readable bit - n = Value at POR  2002 Microchip Technology Inc. 6.1 Timer1 Operation Timer1 can operate in one of these modes: • timer • synchronous counter • asynchronous counter The Operating mode is determined by the clock select bit, TMR1CS (T1CON< ...

Page 34

... The prescaler, however, will continue to increment. TMR1 TMR1L TMR1ON T1SYNC On/Off (2) 1 Prescaler T1OSCEN F /4 OSC Enable Internal 0 (1) Oscillator Clock T1CKPS1:T1CKPS0 TMR1CS Synchronized 0 Clock Input 1 Synchronize det 2 Q Clock  2002 Microchip Technology Inc. ...

Page 35

... Table 6-1 shows the capacitor selection for the Timer1 oscillator. The Timer1 oscillator is identical to the LP oscillator. The user must provide a software time delay to ensure proper oscillator start-up.  2002 Microchip Technology Inc. PIC16F72 TABLE 6-1: CAPACITOR SELECTION FOR THE TIMER1 OSCILLATOR ...

Page 36

... SSPIE CCP1IE TMR2IE Value on Value on Bit 1 Bit 0 all other POR, BOR RESETS INTF RBIF 0000 000x 0000 000u TMR1IF 0000 0000 0000 0000 TMR1IE 0000 0000 0000 0000 xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu  2002 Microchip Technology Inc. ...

Page 37

... The match output of TMR2 goes through a 4-bit postscaler (which gives a 1:1 to 1:16 scaling inclusive) to generate a TMR2 interrupt (latched in flag bit TMR2IF, (PIR1<1>)).  2002 Microchip Technology Inc. 7.2 Timer2 Prescaler and Postscaler The prescaler and postscaler counters are cleared when any of the following occurs: • ...

Page 38

... R/W-0 bit Bit is unknown Value on Value on Bit 1 Bit 0 all other POR, BOR RESETS INTF RBIF 0000 000x 0000 000u TMR2IF TMR1IF -0-- 0000 0000 0000 TMR1IE -0-- 0000 0000 0000 0000 0000 0000 0000 1111 1111 1111 1111  2002 Microchip Technology Inc. ...

Page 39

... CCP1 resets TMR1 and starts an A/D conversion (if A/D module is enabled) 11xx = PWM mode Legend Readable bit - n = Value at POR  2002 Microchip Technology Inc. Additional information on the CCP module is available in the PICmicro™ Mid-Range MCU Reference Manual, (DS33023). TABLE 8-1: CCP Mode ...

Page 40

... EXAMPLE 8-1: CLRF CCP1CON CCPR1L MOVLW NEW_CAPT_PS ; Load the W reg with MOVWF CCP1CON TMR1L CHANGING BETWEEN CAPTURE PRESCALERS ; Turn CCP module off ; the new prescaler ; mode value and CCP ON ; Load CCP1CON with ; this value  2002 Microchip Technology Inc. ...

Page 41

... RC2/CCP1 R pin TRISC<2> Output Enable CCP1CON<3:0> Mode Select  2002 Microchip Technology Inc. 8.2.1 CCP PIN CONFIGURATION The user must configure the RC2/CCP1 pin as an output by clearing the TRISC<2> bit. Note: Clearing the CCP1CON register will force the RC2/CCP1 compare output latch to the default low level ...

Page 42

... RESETS INTF RBIF 0000 000x 0000 000u TMR2IF TMR1IF -0-- 0000 0000 0000 TMR1IE -0-- 0000 0000 0000 1111 1111 1111 1111 xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu  2002 Microchip Technology Inc. ...

Page 43

... PWM OUTPUT Period Duty Cycle TMR2 = PR2 TMR2 = Duty Cycle TMR2 = PR2  2002 Microchip Technology Inc. 8.3.1 PWM PERIOD The PWM period is specified by writing to the PR2 reg- ister. The PWM period can be calculated using the formula in Equation 8-1. EQUATION 8-1: PWM period = [(PR2 • ...

Page 44

... INTF RBIF 0000 000x 0000 000u TMR2IF TMR1IF -0-- 0000 0000 0000 TMR2IE TMR1IE -0-- 0000 0000 0000 1111 1111 1111 1111 0000 0000 0000 0000 1111 1111 1111 1111 xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu  2002 Microchip Technology Inc. ...

Page 45

... MCU Family Reference (DS33023). Refer to Application Note AN578, “Use of the SSP 2 Module in the I C Multi-Master Environment.”  2002 Microchip Technology Inc. 9.2 SPI Mode This section contains operational characteristics of the SPI module. SPI mode allows 8 bits of data to be synchronously transmitted and received simultaneously. To accomplish communication, typically three pins are used: • ...

Page 46

... C mode only) – This bit holds the R/W bit information follow mode only modes Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared R-0 R-0 R-0 R bit 0 ® Bit is unknown  2002 Microchip Technology Inc. ...

Page 47

... C Slave mode, 7-bit address with START and STOP bit interrupts enabled 2 1111 = I C Slave mode, 10-bit address with START and STOP bit interrupts enabled Legend Readable bit - n = Value at POR  2002 Microchip Technology Inc. R/W-0 R/W-0 R/W-0 SSPEN CKP SSPM3 SSPM2 ® ...

Page 48

... PORTA Data Direction Register D R Value on Value on Bit 1 Bit 0 all other POR, BOR RESETS INTF RBIF 0000 000x 0000 000u 1111 1111 1111 1111 xxxx xxxx uuuu uuuu SSPM0 0000 0000 0000 0000 --11 1111 --11 1111 UA BF --00 0000 --00 0000  2002 Microchip Technology Inc. ...

Page 49

... SSPIF FIGURE 9-4: SPI MODE TIMING (SLAVE MODE WITH CKE = 1) SS SCK (CKP = 0) SCK (CKP = 1) SDO bit7 bit6 SDI (SMP = 0) bit7 SSPIF  2002 Microchip Technology Inc. bit6 bit5 bit4 bit3 bit6 bit5 bit3 bit4 bit2 bit5 bit3 bit4 PIC16F72 ...

Page 50

... The SSPSR register value is loaded into the SSPBUF register. b) The buffer full bit set ACK pulse is generated. d) SSP interrupt flag bit, SSPIF (PIR1<3>) is set (interrupt is generated, if enabled the falling edge of the ninth SCL pulse mode, with the SSPEN bit set operation may be  2002 Microchip Technology Inc. ...

Page 51

... Note 1: Shaded cells show the conditions where the user software did not properly clear the overflow condition.  2002 Microchip Technology Inc. 9.3.1.3 When the R/W bit of the incoming address byte is set and an address match occurs, the R/W bit of the SSPSTAT register is set ...

Page 52

... SSPBUF is written in software Set bit after writing to SSPBUF (the SSPBUF must be written to before the CKP bit can be set) Receiving Data ACK Bus Master terminates transfer ACK is not sent. Transmitting Data ACK From SSP Interrupt Service Routine  2002 Microchip Technology Inc. ...

Page 53

... Legend unknown unchanged unimplemented locations read as ‘0’. Shaded cells are not used by SSP module in SPI mode. 2 Note 1: Maintain these bits clear mode.  2002 Microchip Technology Inc. 9.3.3 MULTI-MASTER MODE OPERATION In Multi-Master mode operation, the interrupt genera- tion on the detection of the START and STOP condi- tions allows the determination of when the bus is free ...

Page 54

... PIC16F72 NOTES: DS39597B-page 52  2002 Microchip Technology Inc. ...

Page 55

... A/D converter module is operating 0 = A/D converter module is shut-off and consumes no operating current Legend Readable bit - n = Value at POR  2002 Microchip Technology Inc. The A/D module has three registers: • A/D Result Register • A/D Control Register 0 • A/D Control Register 1 A device RESET forces all registers to their RESET state ...

Page 56

... For next conversion step 1 or step 2 as required. The A/D conversion time per bit is defined as T required before the next acquisition starts. R/W-0 R/W-0 R/W-0 PCFG2 PCFG1 PCFG0 bit 0 V REF V DD RA3 V DD RA3 V DD RA3 Bit is unknown . A minimum wait  2002 Microchip Technology Inc. ...

Page 57

... PIN V = threshold voltage T I leakage = leakage current at the pin due to various junctions R = interconnect resistance sampling switch C = sample/hold capacitance (from DAC) HOLD  2002 Microchip Technology Inc. CHS2:CHS0 V AIN (Input Voltage 000 or 010 or 100 001 or 011 or 101 PCFG2:PCFG0 V DD Sampling ...

Page 58

... AD on the selected channel. The GO/DONE bit can then be set to start the conversion ADCS<1:0> time of 4 µs, but can vary between 2-6 µ will be converted wait AD Maximum Device Frequency Max. 1.25 MHz 5 MHz 20 MHz (Note 1)  2002 Microchip Technology Inc. ...

Page 59

... TRISA — — Legend unknown unchanged unimplemented, read as ‘0’. Shaded cells are not used for A/D conversion.  2002 Microchip Technology Inc. 10.6 Effects of a RESET A device RESET forces all registers to their RESET state. The A/D module is disabled and any conversion in progress is aborted ...

Page 60

... PIC16F72 NOTES: DS39597B-page 58  2002 Microchip Technology Inc. ...

Page 61

... RESET while the power supply stabilizes, and is enabled or disabled using a configuration bit. With these two timers on-chip, most applications need no external RESET circuitry.  2002 Microchip Technology Inc. PIC16F72 SLEEP mode is designed to offer a very low current Power-down mode. The user can wake-up from SLEEP through external RESET, Watchdog Timer Wake-up, or through an interrupt ...

Page 62

... R = Readable bit P = Programmable bit - n = Value when device is unprogrammed DS39597B-page 60 (1) U-1 U-1 u-1 U-1 u-1 — — BOREN — Unimplemented bit, read as ‘1’ Unchanged from programmed state u-1 u-1 u-1 u-1 PWRTEN WDTEN F0SC1 F0SC0 bit0  2002 Microchip Technology Inc. ...

Page 63

... Note 1: See Table 11-1 and Table 11-2 for typical values of C1 and C2 series resistor (RS) may be required for AT strip cut crystals varies with the crystal chosen.  2002 Microchip Technology Inc. FIGURE 11-2: Clock from Ext. System TABLE 11-1: Typical Capacitor Values Used: ...

Page 64

... Table 11-6 for a full description of RESET states of all registers. A simplified block diagram of the on-chip RESET circuit is shown in Figure 11-4. ) values, and the operat- EXT RC OSCILLATOR MODE Internal OSC1 Clock PIC16F72 OSC2/CLKO / Ω ≤ R ≤ 100 k Ω EXT C > EXT  2002 Microchip Technology Inc. ...

Page 65

... MCLR and excessive current beyond the device specification during the ESD event. For this reason, Microchip recommends that the MCLR pin no longer be tied directly The use network, as shown in Figure 11-5, is suggested.  2002 Microchip Technology Inc. PIC16F72 S R FIGURE 11-5: RECOMMENDED MCLR CIRCUIT ...

Page 66

... BOR bit is unpredictable. Bit1 is POR (Power-on Reset Status bit cleared on a Power-on Reset and unaffected otherwise. The user must set this bit following a Power-on Reset. BOR BOR for less BOR . The BOR should fall DD , with the BOR  2002 Microchip Technology Inc. ...

Page 67

... Brown-out Reset Interrupt Wake-up from SLEEP Legend unchanged unknown unimplemented bit, read as '0'. Note 1: When the wake-up is due to an interrupt and the GIE bit is set, the PC is loaded with the interrupt vector (0004h).  2002 Microchip Technology Inc. Power-up Brown-out PWRTEN = 1 1024 T ...

Page 68

... Microchip Technology Inc. (2) (3) (1) (1) ...

Page 69

... DD MCLR INTERNAL POR PWRT TIME-OUT OST TIME-OUT INTERNAL RESET FIGURE 11-8: TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED NETWORK): CASE MCLR INTERNAL POR PWRT TIME-OUT OST TIME-OUT INTERNAL RESET  2002 Microchip Technology Inc PWRT T OST DD T PWRT T OST DD T PWRT T OST PIC16F72 ...

Page 70

... Q cycle. The latency is the same for one or two cycle instructions. Individual interrupt flag bits are set, regardless of the status of their corresponding mask bit, PEIE bit, or the GIE bit. TMR0IF TMR0IE INTF INTE RBIF RBIE PEIE GIE Wake-up (If in SLEEP mode) Interrupt to CPU  2002 Microchip Technology Inc. ...

Page 71

... W into STATUS register SWAPF W_TEMP,F ;Swap W_TEMP SWAPF W_TEMP,W ;Swap W_TEMP into W  2002 Microchip Technology Inc. 11.11.3 PORTB INTCON CHANGE An input change on PORTB<7:4> sets flag bit RBIF (INTCON<0>). The interrupt can be enabled/disabled by setting/clearing enable bit RBIE (INTCON<4>) (see flag ...

Page 72

... Postscaler MUX PSA 0 1 MUX WDT Time-out Bit 6 Bit 5 Bit 4 Bit 3 (1) BOREN — CP PWRTEN INTEDG T0CS T0SE PSA PS2:PS0 To TMR0 (Figure 5-1) PSA Bit 2 Bit 1 Bit 0 (1) WDTEN FOSC1 FOSC0 PS2 PS1 PS0  2002 Microchip Technology Inc. ...

Page 73

... C). 6. A/D conversion (when A/D clock source is RC).  2002 Microchip Technology Inc. Other peripherals cannot generate interrupts since during SLEEP, no on-chip clocks are present. When the SLEEP instruction is being executed, the next instruction ( pre-fetched. For the device to wake-up through an interrupt event, the corresponding interrupt enable bit must be set (enabled) ...

Page 74

... PC+2 PC Inst( Inst( Dummy cycle FIGURE 11-13: External Connector Signals + CLK Data I/O * Isolation devices (as required). 0004h 0005h Inst(0004h) Inst(0005h) Dummy cycle Inst(0004h) TYPICAL IN-CIRCUIT SERIAL PROGRAMMING CONNECTION To Normal Connections * PIC16F72 MCLR/V PP RB6 RB7 * * * Normal Connections  2002 Microchip Technology Inc. ...

Page 75

... MHz, the normal instruction execution time is 1 µ conditional test is true, or the program counter is changed as a result of an instruction, the instruction execution time is 2 µs.  2002 Microchip Technology Inc. Table 12-2 lists the instructions recognized by the MPASM TM assembler ...

Page 76

... TO PD 0000 0110 0100 , 1kkk kkkk kkkk Z 1000 kkkk kkkk 00xx kkkk kkkk 0000 0000 1001 01xx kkkk kkkk 0000 0000 1000 TO PD 0000 0110 0011 , C,DC,Z 110x kkkk kkkk Z 1010 kkkk kkkk  2002 Microchip Technology Inc. ...

Page 77

... Operands: (W) .AND. (k) → (W) Operation: Status Affected: Z Description: The contents of W register are AND’ed with the eight-bit literal ‘k’. The result is placed in the W register.  2002 Microchip Technology Inc. ANDWF k Syntax: Operands: Operation: Status Affected: Description: BCF f,d Syntax: ...

Page 78

... Clear Watchdog Timer Syntax: [ label ] CLRWDT Operands: None 00h → WDT Operation: 0 → WDT prescaler, 1 → → PD Status Affected: TO, PD Description: CLRWDT instruction resets the Watchdog Timer. It also resets the prescaler of the WDT. Status bits TO and PD are set.  2002 Microchip Technology Inc. f ...

Page 79

... If the result is ‘1’, the next instruc- tion is executed. If the result is ‘0’, then a NOP is executed instead, making instruction. CY  2002 Microchip Technology Inc. PIC16F72 GOTO Unconditional Branch Syntax: [ label ] GOTO k 0 ≤ k ≤ 2047 Operands: k → ...

Page 80

... The eight-bit literal ‘k’ is loaded into W register. The don’t cares will assemble as ‘0’s. Move label ] MOVWF f 0 ≤ f ≤ 127 (W) → (f) None Move data from W register to register ‘f’. No Operation [ label ] NOP None No operation None No operation.  2002 Microchip Technology Inc. ...

Page 81

... Status Affected: None Description: Return from subroutine. The stack is POPed and the top of the stack (TOS) is loaded into the program counter. This is a two-cycle instruction.  2002 Microchip Technology Inc. PIC16F72 RLF Rotate Left f through Carry Syntax: [ label ] RLF f,d 0 ≤ f ≤ 127 Operands: d ∈ ...

Page 82

... Operation: Status Affected: Z Description: Exclusive OR the contents of the W register with register ‘f’. If ‘d’ = ‘0’, the result is stored in the W register. If ‘d’ = ‘1’, the result is stored back in register ‘f’.  2002 Microchip Technology Inc. f,d ...

Page 83

... A project manager • Customizable toolbar and key mapping • A status bar • On-line help  2002 Microchip Technology Inc. The MPLAB IDE allows you to: • Edit your source files (either assembly or ‘C’) • One touch assemble (or compile) and download ...

Page 84

... ICEPIC In-Circuit Emulator The ICEPIC low cost, in-circuit emulator is a solution for the Microchip Technology PIC16C5X, PIC16C6X, PIC16C7X and PIC16CXXX families of 8-bit One- Time-Programmable (OTP) microcontrollers. The mod- ular system can support different subsets of PIC16C5X or PIC16CXXX products through the use of inter- changeable personality modules, or daughter boards ...

Page 85

... PIC16C92X PIC17C76X, may be supported with an adapter socket. The PICSTART Plus development programmer is CE compliant.  2002 Microchip Technology Inc. 13.11 PICDEM 1 Low Cost PICmicro Demonstration Board The PICDEM 1 demonstration board is a simple board which demonstrates the capabilities of several of Microchip’s microcontrollers. The microcontrollers sup- ...

Page 86

... Programming Tools K L evaluation and programming tools support EE OQ Microchip’s HCS Secure Data Products. The HCS eval- uation kit includes a LCD display to show changing codes, a decoder to decode transmissions and a pro- gramming interface to program test transmitters.  2002 Microchip Technology Inc. ...

Page 87

... DEVELOPMENT TOOLS FROM MICROCHIP MCP2510 MCRFXXX HCSXXX 93CXX 25CXX/ 24CXX/ PIC18FXXX PIC18CXX2 PIC17C7XX PIC17C4X PIC16C9XX PIC16F8XX PIC16F8X PIC16C8X/ PIC16C7XX PIC16C7X PIC16F62X PIC16CXXX PIC16C6X PIC16C5X PIC14000 PIC12CXXX Tools Software Emulators Debugger Programmers  2002 Microchip Technology Inc. PIC16F72 Kits Eval and Boards Demo DS39597B-page 85 ...

Page 88

... PIC16F72 NOTES: DS39597B-page 86  2002 Microchip Technology Inc. ...

Page 89

... This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability.  2002 Microchip Technology Inc. (except V , MCLR. and RA4) ......................................... -0. (Note 2) ...

Page 90

... PIC16F72 FIGURE 14-1: PIC16F72 (INDUSTRIAL, EXTENDED) VOLTAGE-FREQUENCY GRAPH 6.0V 5.5V 5.0V 4.5V 4.0V 3.5V 3.0V 2.5V 2.0V FIGURE 14-2: PIC16LF72 (INDUSTRIAL) VOLTAGE-FREQUENCY GRAPH 6.0V 5.5V 5.0V 4.5V 4.0V 3.5V 3.0V 2.5V 2. (12 MHz/V) (V MAX Note the minimum voltage of the PICmicro DDAPPMIN ...

Page 91

... DC Characteristics: PIC16F72 (Industrial, Extended) PIC16LF72 (Industrial) PIC16LF72 (Industrial) PIC16F72 (Industrial, Extended) Param Sym Characteristic No. V Supply Voltage DD D001 PIC16LF72 D001 PIC16F72 D001A D002* V RAM Data Retention DR Voltage (Note 1) D003 V V Start Voltage to POR DD ensure internal Power-on Reset signal D004 Rise Rate to ensure ...

Page 92

... PIC16F72 14.1 DC Characteristics: PIC16F72 (Industrial, Extended) PIC16LF72 (Industrial) (Continued) PIC16LF72 (Industrial) PIC16F72 (Industrial, Extended) Param Sym Characteristic No. I Supply Current (Notes D010 PIC16LF72 D010A D010 PIC16F72 D013 ∆I D015* Brown-out Reset Current BOR (Note 6) I Power-down Current (Notes D020 PIC16LF72 D021 ...

Page 93

... DC Characteristics: PIC16F72 (Industrial, Extended) PIC16LF72 (Industrial) DC CHARACTERISTICS Param Sym Characteristic No. V Input Low Voltage IL I/O ports D030 with TTL buffer D030A D031 with Schmitt Trigger buffer D032 MCLR, OSC1 (in RC mode) D033 OSC1 (in XT and LP mode) OSC1 (in HS mode) V Input High Voltage ...

Page 94

... PIC16F72 14.2 DC Characteristics: PIC16F72 (Industrial, Extended) PIC16LF72 (Industrial) (Continued) DC CHARACTERISTICS Param Sym Characteristic No. V Output Low Voltage OL D080 I/O ports D083 OSC2/CLKO (RC osc config) V Output High Voltage OH D090 I/O ports (Note 3) D092 OSC2/CLKO (RC osc config) D150* V Open Drain High Voltage OD Capacitive Loading Specs on Output Pins ...

Page 95

... C specifications only Hold ST DAT DATA input hold STA START condition FIGURE 14-3: LOAD CONDITIONS Load Condition 1 Pin = 464 Ω for all pins except OSC2 for OSC2 output  2002 Microchip Technology Inc specifications only specifications only) T Time osc OSC1 SCK ss SS ...

Page 96

... LP Osc mode — Osc mode — Osc mode — Osc mode — Osc mode ns XT Osc mode 250 ns HS Osc mode — Osc mode 4/F CY OSC — oscillator — oscillator — oscillator oscillator oscillator oscillator  2002 Microchip Technology Inc. ...

Page 97

... Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. †† These parameters are asynchronous events, not related to any internal clock edges. Note 1: Measurements are taken in RC mode, where CLKO output  2002 Microchip Technology Inc ...

Page 98

... — 1024 T — — T OSC OSC 28 72 132 µ s — — 2.1 µ s 100 — —  2002 Microchip Technology Inc. 34 Conditions = 5V, -40°C to +85°C = 5V, -40°C to +85°C = OSC1 period = 5V, -40°C to +85°C ≤ V (D005) BOR ...

Page 99

... TCKEZtmr1 Delay from External Clock Edge to Timer Increment * These parameters are characterized but not tested. † Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested.  2002 Microchip Technology Inc ...

Page 100

... Standard(F) 10 Extended(LF Standard(F) 10 Extended(LF Standard(F) — Extended(LF) — Standard(F) — Extended(LF) — Typ† Max Units Conditions — — ns — — ns — — ns — — ns — — ns — — ns — — prescale value (1  2002 Microchip Technology Inc. ...

Page 101

... Note: Refer to Figure 14-3 for load conditions. FIGURE 14-11: SPI MASTER MODE TIMING (CKE = 1, SMP = SCK (CKP = SCK (CKP = 1) SDO MSb SDI MSb In 74 Note: Refer to Figure 14-3 for load conditions.  2002 Microchip Technology Inc MSb Bit6 - - - - - -1 75, 76 Bit6 - - - - LSb Bit6 - - - - - -1 75, 76 Bit6 - - - -1 LSb In PIC16F72 ...

Page 102

... SPI SLAVE MODE TIMING (CKE = SCK (CKP = 0) 71 SCK (CKP = 1) MSb SDO SDI SDI MSb In 74 Note: Refer to Figure 14-3 for load conditions. DS39597B-page 100 MSb Bit6 - - - - - -1 75, 76 Bit6 - - - - Bit6 - - - - - -1 LSb 75, 76 Bit6 - - - -1 LSb LSb 77 LSb  2002 Microchip Technology Inc. ...

Page 103

... Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. 2 FIGURE 14-14 BUS START/STOP BITS TIMING SCL 91 90 SDA START Condition Note: Refer to Figure 14-3 for load conditions.  2002 Microchip Technology Inc. Characteristic Min 100 100 Standard(F) — ...

Page 104

... Conditions Only relevant for Repeated START condition After this period, the first clock pulse is generated 102 92 110  2002 Microchip Technology Inc. ...

Page 105

... LOW period of the SCL signal. If such a device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line T 2 Standard mode I C bus specification), before the SCL line is released.  2002 Microchip Technology Inc. Min Max 100 kHz mode 4.0 — ...

Page 106

... A/D module current is from the RA3 pin or the V REF 3: The A/D conversion result never decreases with an increase in the input voltage and has no missing codes. DS39597B-page 104 PIC16LF72 (INDUSTRIAL) Min Typ† Max Units — ...

Page 107

... OLD_DATA SAMPLING STOPPED is added before the A/D clock starts. This allows the CY Min Typ† Max Units PIC16F72 1.6 — PIC16LF72 2.0 — PIC16F72 2.0 4.0 PIC16LF72 3.0 6.0 9 — 5* — — — OSC cycle. CY PIC16F72 NEW_DATA DONE Conditions µs ≥ ...

Page 108

... PIC16F72 NOTES: DS39597B-page 106  2002 Microchip Technology Inc. ...

Page 109

... V 2 FIGURE 15-2: MAXIMUM Typical: statistical mean @ 25°C Maximum: mean + 3 (-40°C to +125°C) 6 Minimum: mean – 3 (-40°C to +125° 2002 Microchip Technology Inc. vs. F OVER V (HS MODE) OSC DD 3 vs. F OVER V (HS MODE) OSC PIC16F72 5 ...

Page 110

... F (MHz) OSC vs. F OVER V (XT MODE) OSC DD 1.5 2.0 2.5 F (MHz) OSC 5.5V 5.0V 4.5V 4.0V 3.5V 3.0V 2.5V 2.0V 3.0 3.5 4.0 5.5V 5.0V 4.5V 4.0V 3.5V 3.0V 2.5V 2.0V 3.0 3.5 4.0 2002 Microchip Technology Inc. ...

Page 111

... FIGURE 15-6: MAXIMUM I DD 100 Typical: statistical mean @ 25°C Maximum: mean + 3 (-40°C to +125°C) Minimum: mean – 3 (-40°C to +125° 2002 Microchip Technology Inc. vs. F OVER V (LP MODE) OSC DD 5.5V 5.0V 4.5V 4.0V 3.5V 3.0V 2.5V 2. (kHz) OSC vs ...

Page 112

... DS39597B-page 110 vs. V FOR VARIOUS VALUES Operation above 4 MHz is not recomended 3.5 4.0 4.5 V (V) DD vs. V FOR VARIOUS VALUES Operation above 4 MHz is not recomended 5 100 k 3.5 4.0 4 100 k 5.0 5.5 5.0 5.5 2002 Microchip Technology Inc. ...

Page 113

... DD 100 10 1 0.1 Typical: statistical mean @ 25°C Maximum: mean + 3 (-40°C to +125°C) Minimum: mean – 3 (-40°C to +125°C) 0.01 2.0 2.5 2002 Microchip Technology Inc. vs. V FOR VARIOUS VALUES 3.5 4.0 V (V) DD Max 125°C Max 85°C Typ 25°C 3 ...

Page 114

... DS39597B-page 112 OVER TEMPERATURE Indeterminant State 3.0 3.5 4.0 V (V) DD vs. V OVER TEMPERATURE WDT DD Max (125˚C) Typ (25˚C) 3.0 3.5 4.0 V (V) DD Device in SLEEP Max (125˚C) Typ (25˚C) 4.5 5.0 5.5 4.5 5.0 5.5 2002 Microchip Technology Inc. ...

Page 115

... FIGURE 15-14: AVERAGE WDT PERIOD vs 125°C 35 85°C 30 25° -40° 2.0 2.5 2002 Microchip Technology Inc. (125°C) Typ (25°C) (-40°C) 3.0 3.5 4.0 V (V) DD OVER TEMPERATURE (- +125 C) DD 3.0 3.5 4.0 V (V) DD PIC16F72 (- +125 C) DD Typical: statistical mean @ 25°C Maximum: mean + 3 (-40° ...

Page 116

... DS39597B-page 114 vs (-mA Typical: statistical mean @ 25°C Maximum: mean + 3 (-40°C to +125°C) Minimum: mean – 3 (-40°C to +125°C) Max Typ (25°C) Min (-mA 5V, - +125 C) DD Max Typ (25°C) Min 3V, - +125 2002 Microchip Technology Inc. ...

Page 117

... FIGURE 15-18: TYPICAL, MINIMUM AND MAXIMUM V 3.0 Typical: statistical mean @ 25°C 2.5 Maximum: mean + 3 (-40°C to +125°C) Minimum: mean – 3 (-40°C to +125°C) 2.0 1.5 1.0 0.5 0 2002 Microchip Technology Inc. vs 5V, - +125 Typ (25°C) Min (-40° (-mA ...

Page 118

... INPUT, - +125 Max (-40° Typ (25° Min (125°C) TH 3.0 3.5 4.0 V (V) DD vs. V (ST INPUT, - +125 3.5 4.0 V (V) DD 4.5 5.0 5.5 Max (125°C) IH Min (-40° Max (-40° Min (125°C) IL 4.5 5.0 5.5 2002 Microchip Technology Inc. ...

Page 119

... Standard PICmicro device marking consists of Microchip part number, year code, week code, and traceability code. For PICmicro device marking beyond this, certain price adders apply. Please check with your Microchip Sales Office. For QTP devices, any special marking adders are included in QTP price. 2002 Microchip Technology Inc. PIC16F72 Example PIC16F72-I/SP ...

Page 120

... MILLIMETERS MIN NOM MAX 28 2.54 3.56 3.81 4.06 3.18 3.30 3.43 0.38 7.62 7.87 8.26 6.99 7.24 7.49 34.16 34.67 35.18 3.18 3.30 3.43 0.20 0.29 0.38 1.02 1.33 1.65 0.41 0.48 0.56 8.13 8.89 10. 2002 Microchip Technology Inc. ...

Page 121

... Mold Draft Angle Top Mold Draft Angle Bottom * Controlling Parameter § Significant Characteristic Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010” (0.254mm) per side. JEDEC Equivalent: MS-013 Drawing No. C04-052 2002 Microchip Technology Inc Units INCHES* ...

Page 122

... A2 MILLIMETERS* MIN NOM MAX 28 0.65 1.73 1.85 1.98 1.63 1.73 1.83 0.05 0.15 0.25 7.59 7.85 8.10 5.11 5.25 5.38 10.06 10.20 10.34 0.56 0.75 0.94 0.10 0.18 0.25 0.00 101.60 203.20 0.25 0.32 0. 2002 Microchip Technology Inc. ...

Page 123

... Tie Bar Length Chamfer Mold Draft Angle Top * Controlling Parameter Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010” (0.254mm) per side. JEDEC equivalent: pending Drawing No. C04-114 2002 Microchip Technology Inc. EXPOSED METAL PADS ...

Page 124

... Parameter Drawing No. C04-2114 DS39597B-page 122 B Units INCHES MIN NOM MAX p .026 BSC B .009 .011 .014 L .020 .024 .030 M .005 .006 L p PACKAGE EDGE MILLIMETERS* MIN NOM MAX 0.65 BSC 0.23 0.28 0.35 0.50 0.60 0.75 0.13 0.15 2002 Microchip Technology Inc. ...

Page 125

... Communication Basic SSP/SSP 2 (SPI Slave) Frequency 20 MHz A/D 8-bit, 5 Channels CCP 1 Program Memory 2K EPROM RAM 128 bytes EEPROM Data None Other — 2002 Microchip Technology Inc. PIC16F72 Revision Description PIC16F872 MSSP SSP 2 (SPI Master/Slave) (SPI MHz 20 MHz 10-bit, 5 Channels 8-bit, 5 Channels ...

Page 126

... PIC16F72 NOTES: DS39597B-page 124 2002 Microchip Technology Inc. ...

Page 127

... SSP in SPI Mode ........................................................ 46 Timer0/WDT Prescaler................................................ 29 Timer1 ......................................................................... 32 Timer2 ......................................................................... 35 Watchdog Timer (WDT) .............................................. 70 BOR. See Brown-out Reset Brown-out Reset (BOR) .................................... 59, 62, 65, 66 Buffer Full Status bit, BF ..................................................... 44 2002 Microchip Technology Inc. PIC16F72 C Capture/Compare/PWM ..................................................... 37 Associated Registers with PWM and Timer2.............. 42 Associated Registers, Capture, Compare and Timer1............................................................. 40 Capture CCP1IF ...

Page 128

... MPLAB ICE High Performance Universal In-Circuit Emulator with MPLAB IDE ............................ 82 MPLAB Integrated Development Environment Software .................................................. 81 MPLINK Object Linker/MPLIB Object Librarian .................. 82 O On-Line Support ............................................................... 131 OPCODE Field Descriptions............................................... 73 OPTION_REG Register INTEDG bit ................................................................. 13 PS2:PS0 bits............................................................... 13 PSA bit........................................................................ 13 RBPU bit ..................................................................... 13 T0CS bit...................................................................... 13 T0SE bit ...................................................................... 13 2002 Microchip Technology Inc. ...

Page 129

... SS Pinout Descriptions PIC16F72...................................................................... 6 POP .................................................................................... 19 POR. See Power-on Reset PORTA Associated Registers .................................................. 22 Functions .................................................................... 22 2002 Microchip Technology Inc. PIC16F72 PORTA Register ................................................................... 9 PORTB Associated Registers.................................................. 24 Functions .................................................................... 24 Pull-up Enable (RBPU bit) .......................................... 13 RB0/INT Edge Select (INTEDG bit)............................ 13 RB0/INT Pin, External ................................................ 69 RB7:RB4 Interrupt-on-Change Flag (RBIF bit)........... 14 RB7:RB4 Interrupt-on-Change ...

Page 130

... Prescaler .................................................................... 30 T0CKI ......................................................................... 30 Timer1 Associated Registers .................................................. 34 Asynchronous Counter Mode ..................................... 33 Capacitor Selection..................................................... 33 Counter Operation ...................................................... 32 Interrupt ...................................................................... 33 Operation in Timer Mode ............................................ 32 Oscillator..................................................................... 33 Prescaler .................................................................... 34 Resetting TMR1H, TMR1L Register Pair.................... 34 Resetting Using a CCP Trigger Output....................... 33 Synchronized Counter Mode ...................................... 32 Timer2................................................................................. 35 Interrupt ...................................................................... 35 Operation .................................................................... 35 Output ......................................................................... 35 Prescaler, Postscaler .................................................. 35 2002 Microchip Technology Inc. ...

Page 131

... TMR2 Register ...................................................................... 9 TMR2ON bit ........................................................................ 36 TOUTPS0 bit....................................................................... 36 TOUTPS1 bit....................................................................... 36 TOUTPS2 bit....................................................................... 36 TOUTPS3 bit....................................................................... 36 TRISA Register ............................................................. 10, 21 TRISB Register ............................................................. 10, 23 TRISC Register ............................................................. 10, 25 2002 Microchip Technology Inc. PIC16F72 U UA....................................................................................... 44 Update Address bit, UA ...................................................... 44 W Wake-up from SLEEP................................................... 59, 71 Interrupts .............................................................. 65, 66 MCLR Reset ............................................................... 66 WDT Reset ................................................................. 66 Watchdog Timer (WDT) ...

Page 132

... PIC16F72 NOTES: DS39597B-page 130 2002 Microchip Technology Inc. ...

Page 133

... Microchip Products • Conferences for products, Development Systems, technical information and more • Listing of seminars and events 2002 Microchip Technology Inc. PIC16F72 Systems Information and Upgrade Hot Line The Systems Information and Upgrade Line provides system users a listing of the latest versions of all of Microchip's development systems software products ...

Page 134

... Is there any incorrect or misleading information (what and where)? 7. How would you improve this document? 8. How would you improve our software, systems, and silicon products? DS39597B-page 132 Total Pages Sent FAX: (______) _________ - _________ N Literature Number: DS39597B 2002 Microchip Technology Inc. ...

Page 135

... Register on our web site (www.microchip.com/cn) to receive the most current information on our products. 2002 Microchip Technology Inc. XXX Examples: Pattern a) PIC16F72-04I/SO = Industrial Temp., SOIC package, normal b) PIC16LF72-20I/SS = Industrial Temp., SSOP package, extended range DD c) PIC16F72-20I/ML = Industrial Temp., QFN package, normal range DD PIC16F72 ...

Page 136

... Korea Microchip Technology Korea 168-1, Youngbo Bldg. 3 Floor Samsung-Dong, Kangnam-Ku Seoul, Korea 135-882 Tel: 82-2-554-7200 Fax: 82-2-558-5934 Singapore Microchip Technology Singapore Pte Ltd. 200 Middle Road #07-02 Prime Centre Singapore, 188980 Tel: 65-6334-8870 Fax: 65-6334-8850 Taiwan Microchip Technology (Barbados) Inc., Taiwan Branch 11F-3, No ...

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