PIC16LF72-I/SP Microchip Technology, PIC16LF72-I/SP Datasheet - Page 9

• Manufacturer Part Number: PIC16LF72-I/SP
• Description: IC PIC MCU FLASH 2KX14 28DIP
• Manufacturer: Microchip Technology
• Series: PIC® 16Fr

Specifications of PIC16LF72-I/SP

• Core Size: 8-Bit
• Program Memory Size: 3.5KB (2K x 14)
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Core Processor: PIC
• Speed: 20MHz
• Connectivity: I²C, SPI
• Number Of I /o: 22
• Program Memory Type: FLASH
• Ram Size: 128 x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 5.5 V
• Data Converters: A/D 5x8b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-DIP (0.300", 7.62mm)
• Controller Family/series: PIC16LF
• No. Of I/o's: 22
• Ram Memory Size: 128Byte
• Cpu Speed: 16MHz
• No. Of Timers: 3
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

2.0
There are two memory blocks in the PIC16F72 device.
These are the program memory and the data memory.
Each block has separate buses so that concurrent
access can occur. Program memory and data memory
are explained in this section. Program memory can be
read internally by the user code (see Section 4.0).
The data memory can further be broken down into the
general purpose RAM and the Special Function
Registers (SFRs). The operation of the SFRs that
control the “core” are described here. The SFRs used
to control the peripheral modules are described in the
section discussing each individual peripheral module.
Additional information on device memory may be found
in the PICmicro™ Mid-Range Reference Manual,
(DS33023).
2.1
PIC16F72 devices have a 13-bit program counter capa-
ble of addressing a 8K x 14 program memory space.
The address range for this program memory is 0000h -
07FFh. Accessing a location above the physically
implemented address will cause a wraparound.
The RESET Vector is at 0000h and the Interrupt Vector
is at 0004h.
FIGURE 2-1:
 2002 Microchip Technology Inc.
CALL, RETURN
RETFIE, RETLW
MEMORY ORGANIZATION
Program Memory Organization
On-chip Program
Stack Level 1
Stack Level 8
RESET Vector
Interrupt Vector
Memory
PC<12:0>
PROGRAM MEMORY MAP
AND STACK
13
0000h
0004h
0005h
07FFh
0800h
1FFFh
2.2
The Data Memory is partitioned into multiple banks that
contain the General Purpose Registers and the Special
Function Registers. Bits RP1 (STATUS<6>) and RP0
(STATUS<5>) are the bank select bits.
Each bank extends up to 7Fh (128 bytes). The lower
locations of each bank are reserved for the Special
Function Registers. Above the Special Function Regis-
ters are General Purpose Registers, implemented as
static RAM.
All implemented banks contain SFRs. Some “high use”
SFRs from one bank may be mirrored in another bank,
for code reduction and quicker access (e.g., the
STATUS register is in Banks 0 - 3).
2.2.1
The register file can be accessed either directly, or indi-
rectly, through the File Select Register FSR (see
Section 2.5).
Data Memory Organization
RP1:RP0
GENERAL PURPOSE REGISTER
FILE
00
01
10
11
PIC16F72
DS39597B-page 7
Bank
0
1
2
3