PIC18LF14K50-I/P Microchip Technology, PIC18LF14K50-I/P Datasheet - Page 267
![IC PIC MCU FLASH 16KX10 20-PDIP](/photos/12/13/121303/150-20-dip_sml.jpg)
PIC18LF14K50-I/P
Manufacturer Part Number
PIC18LF14K50-I/P
Description
IC PIC MCU FLASH 16KX10 20-PDIP
Manufacturer
Microchip Technology
Series
PIC® XLP™ 18Fr
Datasheets
1.PIC18F13K50-ISS.pdf
(420 pages)
2.PIC18F13K50-ISS.pdf
(40 pages)
3.PIC18F13K50-ISS.pdf
(10 pages)
4.PIC18F13K50-ISS.pdf
(2 pages)
5.PIC18F14K50-IP.pdf
(422 pages)
Specifications of PIC18LF14K50-I/P
Program Memory Type
FLASH
Program Memory Size
16KB (8K x 16)
Package / Case
20-DIP (0.300", 7.62mm)
Core Processor
PIC
Core Size
8-Bit
Speed
48MHz
Connectivity
I²C, SPI, UART/USART, USB
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
14
Eeprom Size
256 x 8
Ram Size
768 x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 3.6 V
Data Converters
A/D 11x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
PIC18LF
Core
PIC
Data Bus Width
8 bit
Data Ram Size
768 B
Interface Type
EUSART/I2C/MSSP/SPI/USB
Maximum Clock Frequency
48 MHz
Number Of Programmable I/os
15
Number Of Timers
4
Operating Supply Voltage
1.8 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
Through Hole
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, DM164127, DV164126
Minimum Operating Temperature
- 40 C
On-chip Adc
11-ch x 10-bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC18LF14K50-I/P
Manufacturer:
Microchip
Quantity:
450
- PIC18F13K50-ISS PDF datasheet
- PIC18F13K50-ISS PDF datasheet #2
- PIC18F13K50-ISS PDF datasheet #3
- PIC18F13K50-ISS PDF datasheet #4
- PIC18F14K50-IP PDF datasheet #5
- Current page: 267 of 422
- Download datasheet (5Mb)
22.5
The USB module can generate multiple interrupt con-
ditions. To accommodate all of these interrupt
sources, the module is provided with its own interrupt
logic structure, similar to that of the microcontroller.
USB interrupts are enabled with one set of control reg-
isters and trapped with a separate set of flag registers.
All sources are funneled into a single USB interrupt
request, USBIF (PIR2<2>), in the microcontroller’s
interrupt logic.
FIGURE 22-7:
FIGURE 22-8:
2010 Microchip Technology Inc.
Note
Differential Data
USB Interrupts
1:
The control transfer shown here is only an example showing events that can occur for every transaction. Typical control transfers
will spread across multiple frames.
USB Reset
URSTIF
RESET
UEIR (Flag) and UEIE (Enable) Registers
CRC5EE
CRC5EF
Start-of-Frame (SOF)
BTOEE
BTSEE
BTOEF
BTSEF
Second Level USB Interrupts
PIDEE
PIDEF
CRC16EF
CRC16EE
USB INTERRUPT LOGIC FUNNEL
EXAMPLE OF A USB TRANSACTION AND INTERRUPT EVENTS
DFN8EE
DFN8EF
(USB Error Conditions)
SOFIF
SOF
SETUP
DATA
Preliminary
STATUS
Figure 22-7 shows the interrupt logic for the USB
module. There are two layers of interrupt registers in
the USB module. The top level consists of overall USB
Status interrupts; these are enabled and flagged in the
UIE and UIR registers, respectively. The second level
consists of USB error conditions, which are enabled
and flagged in the UEIR and UEIE registers. An
interrupt condition in any of these triggers a USB Error
Interrupt Flag (UERRIF) in the top level.
Interrupts may be used to trap routine events in a USB
transaction. Figure 22-8 shows some common events
within a USB frame and their corresponding interrupts.
SETUP Token
STALLIE
STALLIF
UERRIE
UERRIF
ACTVIF
ACTVIE
URSTIE
OUT Token
URSTIF
Control Transfer
IDLEIE
From Host
IN Token
IDLEIF
From Host
SOFIE
TRNIE
From Host
SOFIF
TRNIF
UIR (Flag) and UIE (Enable) Registers
Top Level USB Interrupts
PIC18F/LF1XK50
(USB Status Interrupts)
Empty Data
Transaction
From Host
From Host
To Host
(1)
Data
Data
From Host
To Host
To Host
ACK
ACK
ACK
SOF
1 ms Frame
USBIF
DS41350D-page 267
Set TRNIF
Set TRNIF
Set TRNIF
Transaction
Complete
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