PIC18F46K20-I/PT Microchip Technology, PIC18F46K20-I/PT Datasheet
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... PIC18F23K20/24K20/25K20/26K20 43K20/44K20/45K20/46K20 with 10-Bit A/D and nanoWatt Technology © 2008 Microchip Technology Inc. Data Sheet Flash Microcontrollers Preliminary DS41303D ...
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... PowerMate, PowerTool, REAL ICE, rfLAB, Select Mode, Total Endurance, UNI/O, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. ...
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... Independent input multiplexing • Programmable On-Chip Voltage Reference (CV ) module (% REF DD © 2008 Microchip Technology Inc. PIC18F2XK20/4XK20 Flexible Oscillator Structure: • Four Crystal modes MHz • 4X Phase Lock Loop (available for crystal and internal oscillators) • Two External RC modes MHz • Two External Clock modes MHz • ...
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... PIC18F25K20 32K 16384 PIC18F26K20 64k 32768 PIC18F43K20 8K 4096 PIC18F44K20 16K 8192 PIC18F45K20 32K 16384 PIC18F46K20 64k 32768 Note 1: One pin is input only. 2: Channel count includes internal fixed voltage reference channel. DS41303D-page 2 Data Memory 10-bit CCP/ (1) I/O A/D ECCP EEPROM (2) ...
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... RA4/T0CKI/C1OUT RA5/AN4/SS/HLVDIN/C2OUT RE0/RD/AN5 RE1/WR/AN6 RE2/CS/AN7 V V OSC1/CLKIN/RA7 OSC2/CLKOUT/RA6 RC0/T1OSO/T13CKI RC1/T1OSI/CCP2 RC2/CCP1/P1A RC3/SCK/SCL RD0/PSP0 RD1/PSP1 28-pin QFN RA2/AN2/V -/CV /C2IN+ REF REF RA3/AN3/V +/C1IN+ REF RA4/T0CKI/C1OUT RA5/AN4/SS/HLVDIN/C2OUT OSC1/CLKIN/RA7 OSC2/CLKOUT/RA6 Note 1: RB3 is the alternate pin for CCP2 multiplexing. © 2008 Microchip Technology Inc. PIC18F2XK20/4XK20 ( ...
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... Note 1: RB3 is the alternate pin for CCP2 multiplexing. DS41303D-page PIC18F43K20 PIC18F44K20 28 6 PIC18F45K20 27 7 PIC18F46K20 PIC18F43K20 30 4 PIC18F44K20 PIC18F45K20 PIC18F46K20 Preliminary NC RC0/T1OSO/T13CKI OSC2/CLKOUT/RA6 OSC1/CLKIN/RA7 RE2/CS/AN7 RE1/WR/AN6 RE0/RD/AN5 RA5/AN4/SS/HLVDIN/C2OUT RA4/T0CKI/C1OUT OSC2/CLKOUT/RA6 OSC1/CLKIN/RA7 RE2/CS/AN7 RE1/WR/AN6 RE0/RD/AN5 RA5/AN4/SS/HLVDIN/C2OUT RA4/T0CKI/C1OUT © 2008 Microchip Technology Inc. ...
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... NC 29 — — — – Note 1: CCP2 multiplexed with RB3 when CONFIG3H<0> CCP2 multiplexed with RC1 when CONFIG3H<0> Input only. © 2008 Microchip Technology Inc. PIC18F2XK20/4XK20 — — — — — — — — — — — — — — ...
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... T13CKI (2) CCP2 T1OSI CCP1/ P1A SCK/ SCL SDI/ SDA SDO TX/CK RX/DT Preliminary OSC2/ CLKOUT OSC1/ CLKIN INT0 Yes INT1 Yes INT2 Yes Yes KBI0 Yes KBI1 Yes PGM KBI2 Yes PGC KBI3 Yes PGD MCLR © 2008 Microchip Technology Inc. ...
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... Packaging Information............................................................................................................................................................. 401 Appendix A: Revision History............................................................................................................................................................ 413 Appendix B: Device Differences ....................................................................................................................................................... 414 Index ................................................................................................................................................................................................. 415 The Microchip Web Site.................................................................................................................................................................... 425 Customer Change Notification Service ............................................................................................................................................. 425 Customer Support ............................................................................................................................................................................. 425 Reader Response ............................................................................................................................................................................. 426 Product Identification System ........................................................................................................................................................... 427 © 2008 Microchip Technology Inc. PIC18F2XK20/4XK20 Preliminary DS41303D-page 7 ...
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... When contacting a sales office or the literature center, please specify which device, revision of silicon and data sheet (include literature number) you are using. Customer Notification System Register on our web site at www.microchip.com/cn to receive the most current information on all of our products. DS41303D-page 8 Preliminary © 2008 Microchip Technology Inc. ...
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... PIC18F23K20 • PIC18F43K20 • PIC18F24K20 • PIC18F44K20 • PIC18F25K20 • PIC18F45K20 • PIC18F26K20 • PIC18F46K20 This family offers the advantages of all PIC18 microcontrollers – namely, high performance at an economical price – with the addition of high-endurance, Flash program memory. On top of ...
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... All other features for devices in this family are identical. These are summarized in Table 1-1. The pinouts for all devices are listed in the pin summary tables: Table 1 and Table 2, and I/O description tables: Table 1-2 and Table 1-3. Preliminary © 2008 Microchip Technology Inc. (8 Kbytes for AND 64 Kbytes for ...
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... TABLE 1-1: DEVICE FEATURES © 2008 Microchip Technology Inc. PIC18F2XK20/4XK20 Preliminary DS41303D-page 11 ...
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... RA0/AN0 RA1/AN1 RA2/AN2/V -/CV REF REF RA3/AN3/V + REF RA4/T0CKI/C1OUT RA5/AN4/SS/HLVDIN/C2OUT (3) OSC2/CLKOUT /RA6 (3) OSC1/CLKIN /RA7 PORTB RB0/INT0/FLT0/AN12 RB1/INT1/AN10/C12IN3- RB2/INT2/AN8 (1) RB3/AN9/CCP2 /C12IN2- RB4/KBI0/AN11 RB5/KBI1/PGM RB6/KBI2/PGC RB7/KBI3/PGD PORTC RC0/T1OSO/T13CKI (1) RC1/T1OSI/CCP2 RC2/CCP1 RC3/SCK/SCL RC4/SDI/SDA RC5/SDO RC6/TX/CK RC7/RX/DT PORTE (2) MCLR/V /RE3 PP FVR © 2008 Microchip Technology Inc. ...
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... OSC1/CLKIN and OSC2/CLKOUT are only available in select oscillator modes and when these pins are not being used as digital I/O. Refer to Section 2.0 “Oscillator Module (With Fail-Safe Clock Monitor)” for additional information. © 2008 Microchip Technology Inc. PIC18F2XK20/4XK20 Data Bus<8> Data Latch ...
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... Crystal Oscillator mode O — mode, OSC2 pin outputs CLKOUT which has 1/4 the frequency of OSC1 and denotes the instruction cycle rate I/O TTL General purpose I/O pin CMOS = CMOS compatible input or output I = Input P = Power Preliminary Description © 2008 Microchip Technology Inc. ...
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... Legend: TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels O = Output Note 1: Default assignment for CCP2 when Configuration bit CCP2MX is set. 2: Alternate assignment for CCP2 when Configuration bit CCP2MX is cleared. © 2008 Microchip Technology Inc. PIC18F2XK20/4XK20 Pin Buffer Type Type PORTA is a bidirectional I/O port ...
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... Interrupt-on-change pin I/O ST In-Circuit Debugger and ICSP™ programming clock pin I/O TTL Digital I/O I TTL Interrupt-on-change pin I/O ST In-Circuit Debugger and ICSP™ programming data pin CMOS = CMOS compatible input or output I = Input P = Power Preliminary Description © 2008 Microchip Technology Inc. ...
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... Legend: TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels O = Output Note 1: Default assignment for CCP2 when Configuration bit CCP2MX is set. 2: Alternate assignment for CCP2 when Configuration bit CCP2MX is cleared. © 2008 Microchip Technology Inc. PIC18F2XK20/4XK20 Pin Buffer Type Type PORTC is a bidirectional I/O port ...
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... Crystal Oscillator mode O — mode, OSC2 pin outputs CLKOUT which has 1/4 the frequency of OSC1 and denotes the instruction cycle rate I/O TTL General purpose I/O pin CMOS = CMOS compatible input or output I = Input P = Power Preliminary Description © 2008 Microchip Technology Inc. ...
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... Legend: TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels O = Output Note 1: Default assignment for CCP2 when Configuration bit CCP2MX is set. 2: Alternate assignment for CCP2 when Configuration bit CCP2MX is cleared. © 2008 Microchip Technology Inc. PIC18F2XK20/4XK20 Pin Buffer Type Type PORTA is a bidirectional I/O port ...
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... Interrupt-on-change pin I/O ST In-Circuit Debugger and ICSP™ programming clock pin 17 I/O TTL Digital I/O I TTL Interrupt-on-change pin I/O ST In-Circuit Debugger and ICSP™ programming data pin CMOS = CMOS compatible input or output I = Input P = Power Preliminary Description © 2008 Microchip Technology Inc. ...
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... Legend: TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels O = Output Note 1: Default assignment for CCP2 when Configuration bit CCP2MX is set. 2: Alternate assignment for CCP2 when Configuration bit CCP2MX is cleared. © 2008 Microchip Technology Inc. PIC18F2XK20/4XK20 Pin Buffer Type Type PORTC is a bidirectional I/O port ...
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... Enhanced CCP1 output 4 I/O ST Digital I/O I/O TTL Parallel Slave Port data O — Enhanced CCP1 output 5 I/O ST Digital I/O I/O TTL Parallel Slave Port data O — Enhanced CCP1 output CMOS = CMOS compatible input or output I = Input P = Power Preliminary Description © 2008 Microchip Technology Inc. ...
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... Legend: TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels O = Output Note 1: Default assignment for CCP2 when Configuration bit CCP2MX is set. 2: Alternate assignment for CCP2 when Configuration bit CCP2MX is cleared. © 2008 Microchip Technology Inc. PIC18F2XK20/4XK20 Pin Buffer Type Type ...
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... PIC18F2XK20/4XK20 NOTES: DS41303D-page 24 Preliminary © 2008 Microchip Technology Inc. ...
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... Internal Oscillator Block 16 MHz Source 16 MHz (HFINTOSC) 31 kHz Source 31 kHz (LFINTOSC) Note 1: Operates only when HFINTOSC is the primary oscillator. © 2008 Microchip Technology Inc. PIC18F2XK20/4XK20 The Oscillator module can be configured in one of ten primary clock modes Low-Power Crystal 2. XT Crystal/Resonator 3. HS High-Speed Crystal/Resonator 4 ...
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... T1OSCEN bit is set recommended that the Timer1 oscillator be operating and stable before selecting the secondary clock source or a very long delay may occur while the Timer1 oscillator starts. Preliminary © 2008 Microchip Technology Inc. ...
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... Secondary (Timer1) oscillator 00 = Primary clock (determined by CONFIG1H[FOSC<3:0>]). Note 1: Reset state depends on state of the IESO Configuration bit. 2: Source selected by the INTSRC bit of the OSCTUNE register, see text. 3: Default output frequency of HFINTOSC on Reset. © 2008 Microchip Technology Inc. PIC18F2XK20/4XK20 R/W-1 R-q R-0 (1) IRCF0 OSTS IOFS U = Unimplemented bit, read as ‘ ...
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... MHz FIGURE 2-2: EXTERNAL CLOCK (EC) MODE OPERATION Clock from Ext. System I/O Note 1: Alternate pin functions are listed in Section 1.0 “Device Overview”. Preliminary © 2008 Microchip Technology Inc. Oscillator Delay ) WARM OSC1/CLKIN ® PIC MCU (1) OSC2/CLKOUT ...
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... The value of R varies with the Oscillator mode F selected (typically between 2 MΩ MΩ). © 2008 Microchip Technology Inc. PIC18F2XK20/4XK20 Note 1: Quartz crystal characteristics vary according to type, package and manufacturer. The user should consult the manufacturer data sheets for specifications and recommended application ...
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... Speed Start-up and Fail-Safe mode. • FOSC<3:0> of CONFIG1H selects the internal oscillator as the primary clock The HF Internal Oscillator (IOFS) bit of the OSCCON register indicates whether the HFINTOSC is stable or not. Preliminary (High-Frequency Internal via software using the (Low-Frequency Internal © 2008 Microchip Technology Inc. ...
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... The PLLEN bit is active only when the HFINTOSC is the primary clock source (FOSC<2:0> = 100X) and the selected frequency is 8 MHz or 16 MHz. Otherwise, the PLLEN bit is unavailable and always reads ‘0’. © 2008 Microchip Technology Inc. PIC18F2XK20/4XK20 (PWRT), Watchdog Timer (WDT), Fail-Safe Clock Mon- itor (FSCM) and peripherals, are not affected by the change in frequency ...
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... OSCTUNE register. If the measured time is much less than the calculated time, the internal oscillator block is running too slow; to compensate, increment the OSCTUNE register. Preliminary © 2008 Microchip Technology Inc. ...
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... F OUT Osc Loop Filter ÷4 VCO © 2008 Microchip Technology Inc. PIC18F2XK20/4XK20 2.6.2 PLL IN HFINTOSC MODES The 4x frequency multiplier can be used with the inter- nal oscillator block to produce faster device clock speeds than are normally possible with an internal oscillator. When enabled, the PLL produces a clock speed MHz ...
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... OSC1 Pin At logic low (clock/4 output) Configured as PORTA, bit 6 Configured as PORTA, bit 6 Configured as PORTA, bit 6 At logic low (clock/4 output) Feedback inverter disabled at quiescent voltage level Preliminary (parameter 38, CSD OSC2 Pin © 2008 Microchip Technology Inc. ...
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... In particular, when the primary oscillator is the source of the primary clock, OSTS indicates that the Oscillator Start-up Timer (OST) has timed out for LP modes. © 2008 Microchip Technology Inc. PIC18F2XK20/4XK20 2.9.3 CLOCK SWITCH TIMING When switching between one oscillator and another, the new oscillator may not be operating which saves power (see Figure 2-7) ...
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... FOSC<2:0> bits in CONFIG1H Configuration register, or the internal oscillator. OSTS = 0 when the external oscillator is not ready, which indicates that the system is running from the internal oscillator. Preliminary © 2008 Microchip Technology Inc. ...
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... High Speed Old Clock Start-up Time New Clock New Clk Ready Select Old IRCF <2:0> System Clock Note 1: Start-up time includes T OST © 2008 Microchip Technology Inc. PIC18F2XK20/4XK20 (1) Clock Sync Select New (1) Clock Sync Select New (1024 T ) for external clocks, plus T (approx ...
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... Reset or Sleep). After an appropriate amount of time, the user should check the OSTS bit of the OSCCON register to verify the oscillator start-up and that the system clock completed. Preliminary switchover has successfully © 2008 Microchip Technology Inc. ...
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... Legend unknown unchanged, – = unimplemented locations read as ‘0’. Shaded cells are not used by oscillators. Note 1: Other (non Power-up) Resets include MCLR Reset and Watchdog Timer Reset during normal operation. © 2008 Microchip Technology Inc. PIC18F2XK20/4XK20 Oscillator Failure Test Test ...
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... PIC18F2XK20/4XK20 NOTES: DS41303D-page 40 Preliminary © 2008 Microchip Technology Inc. ...
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... Note 1: IDLEN reflects its value when the SLEEP instruction is executed. 2: Includes HFINTOSC and HFINTOSC postscaler, as well as the LFINTOSC source. © 2008 Microchip Technology Inc. PIC18F2XK20/4XK20 3.1.1 CLOCK SOURCES The SCS<1:0> bits allow the selection of one of three clock sources for power-managed modes. They are: • ...
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... Figure 2-7). When the clock switch is complete, the T1RUN bit is cleared, the OSTS bit is set and the primary clock is providing the main system clock. The Timer1 oscillator continues to run as long as the T1OSCEN bit is set. Preliminary © 2008 Microchip Technology Inc. ...
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... Section 2.5.2 “HFINTOSC” are met. The LFINTOSC source will continue to run if any of the conditions noted in Section 2.5.3 “LFIN- TOSC” are met. © 2008 Microchip Technology Inc. PIC18F2XK20/4XK20 3.3 Sleep Mode The Power-Managed Sleep mode in the PIC18F2XK20/ 4XK20 devices is identical to the legacy Sleep mode ® ...
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... TRANSITION TIMING FOR WAKE FROM SLEEP (HSPLL) Q1 OSC1 (1) T OST PLL Clock Output CPU Clock Peripheral Clock Program Counter Wake Event Note1 1024 (approx). These intervals are not shown to scale. OST OSC PLL DS41303D-page (1) T PLL OSTS bit set Preliminary © 2008 Microchip Technology Inc. ...
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... OSC1 CPU Clock Peripheral Clock Program Counter Wake Event © 2008 Microchip Technology Inc. PIC18F2XK20/4XK20 3.4.2 SEC_IDLE MODE In SEC_IDLE mode, the CPU is disabled but the peripherals continue to be clocked from the Timer1 oscillator. This mode is entered from SEC_RUN by set- ting the IDLEN bit and executing a SLEEP instruction. If the device is in another Run mode, set the IDLEN bit first, then set the SCS< ...
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... The exit delay time from Reset to the start of code execution depends on both the clock sources before and after the wake-up and the type of oscillator. Exit delays are summarized in Table 3-3. Preliminary following the wake event CSD mode (see Section 3.2 “Run © 2008 Microchip Technology Inc. ...
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... Oscillator Start-up Timer (parameter 32). t OST 4: Execution continues during the HFINTOSC stabilization period, T © 2008 Microchip Technology Inc. PIC18F2XK20/4XK20 In these instances, the primary clock source either does not require an oscillator start-up delay since it is already running (PRI_IDLE), or normally does not require an oscillator start-up delay (RC, EC, INTOSC, and INTOSCIO modes) ...
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... PIC18F2XK20/4XK20 NOTES: DS41303D-page 48 Preliminary © 2008 Microchip Technology Inc. ...
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... LFINTOSC 11-bit Ripple Counter Note 1: See Table 4-2 for time-out situations. 2: PWRT and OST counters are reset by POR and BOR. See Sections 4.3 and 4.4. © 2008 Microchip Technology Inc. PIC18F2XK20/4XK20 A simplified block diagram of the On-Chip Reset Circuit is shown in Figure 4-1. ...
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... It is recommended that the POR bit be set after a Power-on Reset has been detected so that subsequent Power-on Resets may be detected. DS41303D-page 50 R/W-1 R-1 R Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) (2) (3) Preliminary R/W-0 R/W-0 (2) POR BOR bit Bit is unknown © 2008 Microchip Technology Inc. ...
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... POR occurs; it does not change for any other Reset event. POR is not reset to ‘1’ by any hardware event. To capture multiple events, the user must manually set the bit to ‘1’ by software following any POR. © 2008 Microchip Technology Inc. PIC18F2XK20/4XK20 FIGURE 4-2: EXTERNAL POWER-ON ...
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... Sleep. If the BOR is disabled, in software or by reentering Sleep before the FVR stabilizes, the BOR circuit will not sense a BOR condition. The FVRST bit of the CVRCON2 register can be used to determine FVR stability. BOR Operation Preliminary and operates as previously © 2008 Microchip Technology Inc. ...
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... INTIO1, INTIO2 66 ms Note (65.5 ms) is the nominal Power-up Timer (PWRT) delay the nominal time required for the PLL to lock. © 2008 Microchip Technology Inc. PIC18F2XK20/4XK20 The OST time-out is invoked only for XT, LP, HS and HSPLL modes and only on Power-on Reset exit ...
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... PWRT TIME-OUT OST TIME-OUT INTERNAL RESET FIGURE 4-5: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED MCLR INTERNAL POR PWRT TIME-OUT OST TIME-OUT INTERNAL RESET DS41303D-page 54 T PWRT T OST T PWRT T OST T PWRT T OST Preliminary © 2008 Microchip Technology Inc RISE < PWRT ): CASE CASE 2 DD ...
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... TIME-OUT SEQUENCE ON POR W/PLL ENABLED (MCLR TIED MCLR INTERNAL POR PWRT TIME-OUT OST TIME-OUT PLL TIME-OUT INTERNAL RESET Note 1024 clock cycles. OST ≈ max. First three stages of the PWRT timer. T PLL © 2008 Microchip Technology Inc. PIC18F2XK20/4XK20 , V RISE > PWRT T OST T PWRT T OST ...
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... Special Function Registers. These are categorized by Power-on and Brown-out Resets, Master Clear and WDT Resets and WDT wake-ups. RCON Register SBOREN 0000h (2) 0000h (2) 0000h (2) 0000h (2) 0000h (2) 0000h (2) 0000h (2) 0000h (2) 0000h (2) 0000h ( (1) ( Preliminary STKPTR Register POR BOR STKFUL STKUNF © 2008 Microchip Technology Inc. ...
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... Bits 6 and 7 of PORTA, LATA and TRISA are enabled, depending on the oscillator mode selected. When not enabled as PORTA pins, they are disabled and read ‘0’. 6: All bits of the ANSELH register initialize to ‘0’ if the PBADEN bit of CONFIG3H is ‘0’. © 2008 Microchip Technology Inc. PIC18F2XK20/4XK20 MCLR Resets, Power-on Reset, ...
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... Preliminary © 2008 Microchip Technology Inc. Wake-up via WDT or Interrupt ---- uuuu uuuu uuuu ---- uuuu N/A N/A N/A N/A N/A ---- uuuu ...
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... PIC18F2XK20 PIC18F4XK20 TXSTA PIC18F2XK20 PIC18F4XK20 RCSTA PIC18F2XK20 PIC18F4XK20 EEADR PIC18F2XK20 PIC18F4XK20 EEADRH PIC18F26K20 PIC18F46K20 EEDATA PIC18F2XK20 PIC18F4XK20 EECON2 PIC18F2XK20 PIC18F4XK20 EECON1 PIC18F2XK20 PIC18F4XK20 Legend unchanged unknown unimplemented bit, read as ‘0’ value depends on condition. Shaded cells indicate conditions do not apply for the designated device. ...
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... Preliminary © 2008 Microchip Technology Inc. Wake-up via WDT or Interrupt uuuu uuuu (1) uuuu uuuu uuuu uuuu uuuu uuuu -uuu uuuu (1) uuuu uuuu (1) ...
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... Bits 6 and 7 of PORTA, LATA and TRISA are enabled, depending on the oscillator mode selected. When not enabled as PORTA pins, they are disabled and read ‘0’. 6: All bits of the ANSELH register initialize to ‘0’ if the PBADEN bit of CONFIG3H is ‘0’. © 2008 Microchip Technology Inc. PIC18F2XK20/4XK20 MCLR Resets, Power-on Reset, ...
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... PIC18F2XK20/4XK20 NOTES: DS41303D-page 62 Preliminary © 2008 Microchip Technology Inc. ...
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... PIC18F24K20, PIC18F44K20: 16 Kbytes of Flash Memory 8,192 single-word instructions • PIC18F25K20, PIC18F45K20: 32 Kbytes of Flash Memory 16,384 single-word instructions • PIC18F26K20, PIC18F46K20: 64 Kbytes of Flash Memory 37,768 single-word instructions PIC18 devices have two interrupt vectors. The Reset vector address is at 0000h and the interrupt vector addresses are at 0008h and 0018h ...
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... The user must disable the global interrupt enable bits while accessing the stack to prevent inadvertent stack corruption. Return Address Stack <20:0> 11111 11110 11101 TOSL 34h 00011 001A34h 00010 Top-of-Stack 000D58h 00001 00000 Preliminary Stack Pointer STKPTR<4:0> 00010 © 2008 Microchip Technology Inc. ...
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... SP<4:0>: Stack Pointer Location bits Note 1: Bit 7 and bit 6 are cleared by user software POR. © 2008 Microchip Technology Inc. PIC18F2XK20/4XK20 When the stack has been popped enough times to unload the stack, the next pop will return a value of zero to the PC and sets the STKUNF bit, while the Stack Pointer remains at zero ...
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... Table Latch (TABLAT) register contains the data that is read from or written to program memory. Data is transferred to or from program memory one byte at a time. Table read and table write operations are discussed further in Section 6.1 “Table Reads and Table Writes”. Preliminary © 2008 Microchip Technology Inc. nn ...
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... Instruction @ address SUB_1 All instructions are single cycle, except for any program branches. These take two cycles since the fetch instruction is “flushed” from the pipeline while the new instruction is being fetched and then executed. © 2008 Microchip Technology Inc. PIC18F2XK20/4XK20 5.2.2 INSTRUCTION FLOW/PIPELINING An “ ...
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... RAM location 0? REG1, REG2 ; Yes, execute this word ; 2nd word of instruction REG3 ; continue code Preliminary address embedded into the 0006h is encoded in the program Word Address ↓ 000000h 000002h 000004h 000006h 000008h 00000Ah 00000Ch 00000Eh 000010h 000012h 000014h © 2008 Microchip Technology Inc. ...
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... SFRs and the lower portion of GPR Bank 0 without using the Bank Select Register (BSR). Section 5.3.2 “Access Bank” provides a detailed description of the Access RAM. © 2008 Microchip Technology Inc. PIC18F2XK20/4XK20 5.3.1 BANK SELECT REGISTER (BSR) ...
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... Bank 0). The second 160 bytes are Special Function Registers (from Bank 15). When ‘a’ The BSR specifies the Bank used by the instruction. Access Bank 00h Access RAM Low 5Fh 60h Access RAM High (SFRs) FFh © 2008 Microchip Technology Inc. ...
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... FFh = 1100 00h Bank 12 FFh = 1101 00h Bank 13 FFh 00h = 1110 Bank 14 FFh 00h = 1111 Bank 15 FFh © 2008 Microchip Technology Inc. PIC18F2XK20/4XK20 Data Memory Map 000h Access RAM 05Fh 060h GPR 0FFh 100h GPR 1FFh 200h GPR 2FFh 300h 3FFh ...
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... Bank 0). The second 160 bytes are Special Function Registers (from Bank 15). When ‘a’ The BSR specifies the Bank used by the instruction. Access Bank 00h Access RAM Low 5Fh 60h Access RAM High (SFRs) FFh © 2008 Microchip Technology Inc. ...
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... FFh = 1100 00h Bank 12 FFh = 1101 00h Bank 13 FFh 00h = 1110 Bank 14 FFh 00h = 1111 Bank 15 FFh © 2008 Microchip Technology Inc. PIC18F2XK20/4XK20 Data Memory Map 000h Access RAM 05Fh 060h GPR 0FFh 100h GPR 1FFh 200h GPR 2FFh 300h GPR ...
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... The MOVFF instruction embeds the entire 12-bit address in the instruction. DS41303D-page 74 Data Memory 000h 7 00h Bank 0 1 FFh 100h 00h Bank 1 FFh 200h 00h Bank 2 FFh 300h 00h Bank 3 through Bank 13 FFh E00h 00h Bank 14 FFh F00h 00h Bank 15 FFFh FFh Preliminary (2) From Opcode © 2008 Microchip Technology Inc. ...
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... The mapping of the Access Bank is slightly different when the extended instruction set is enabled (XINST Configuration bit = 1). This is discussed in more detail in Section 5.5.3 “Mapping the Access Bank in Indexed Literal Offset Mode”. © 2008 Microchip Technology Inc. PIC18F2XK20/4XK20 5.3.3 GENERAL PURPOSE REGISTER FILE PIC18 devices may have banked memory in the GPR area ...
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... FB1h FD8h STATUS FB0h Note 1: This is not a physical register. 2: Unimplemented registers are read as ‘0’. 3: This register is not available on PIC18F2XK20 devices. 4: This register is only implemented in the PIC18F46K20 and PIC18F26K20 devices. DS41303D-page 76 Name Address Name TMR0H FAFh SPBRG TMR0L FAEh RCREG T0CON ...
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... RA6/RA7 and their associated latch and direction bits are individually configured as port pins based on various primary oscillator modes. When disabled, these bits read as ‘0’. 6: All bits of the ANSELH register initialize to ‘0’ if the PBADEN bit of CONFIG3H is ‘0’. 7: This register is only implemented in the PIC18F46K20 and PIC18F26K20 devices. © 2008 Microchip Technology Inc. PIC18F2XK20/4XK20 Bit 4 Bit 3 ...
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... RA6/RA7 and their associated latch and direction bits are individually configured as port pins based on various primary oscillator modes. When disabled, these bits read as ‘0’. 6: All bits of the ANSELH register initialize to ‘0’ if the PBADEN bit of CONFIG3H is ‘0’. 7: This register is only implemented in the PIC18F46K20 and PIC18F26K20 devices. DS41303D-page 78 Bit 4 Bit 3 Bit 2 ...
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... RA6/RA7 and their associated latch and direction bits are individually configured as port pins based on various primary oscillator modes. When disabled, these bits read as ‘0’. 6: All bits of the ANSELH register initialize to ‘0’ if the PBADEN bit of CONFIG3H is ‘0’. 7: This register is only implemented in the PIC18F46K20 and PIC18F26K20 devices. © 2008 Microchip Technology Inc. PIC18F2XK20/4XK20 Bit 4 Bit 3 ...
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... Table 24-2 and Table 24-3. Note: The C and DC bits operate as the borrow and digit borrow bits, respectively, in subtraction. R/W-x R/W-x R/W Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) Preliminary R/W-x R/W-x (1) ( bit Bit is unknown (1) © 2008 Microchip Technology Inc. ...
Page 83
... Purpose Register File” location in the Access Bank (Section 5.3.2 “Access Bank”) as the data source for the instruction. © 2008 Microchip Technology Inc. PIC18F2XK20/4XK20 The Access RAM bit ‘a’ determines how the address is interpreted. When ‘a’ is ‘1’, the contents of the BSR (Section 5.3.1 “ ...
Page 84
... W nor the FSR is actually changed in the operation. Accessing the other virtual registers changes the value of the FSR register. ADDWF, INDF1, 1 FSR1H:FSR1L Preliminary 000h Bank 0 100h Bank 1 200h Bank 2 300h 0 Bank 3 through Bank 13 E00h Bank 14 F00h Bank 15 FFFh Data Memory © 2008 Microchip Technology Inc. ...
Page 85
... The SFR map remains the same. Core PIC18 instructions can still operate in both Direct and Indirect Addressing mode; inherent and literal instructions do not change at all. Indirect addressing with FSR0 and FSR1 also remain unchanged. © 2008 Microchip Technology Inc. PIC18F2XK20/4XK20 5.5.1 INDEXED ADDRESSING WITH LITERAL OFFSET ...
Page 86
... F00h Bank 15 F60h SFRs FFFh Data Memory BSR 000h 00000000 060h Bank 0 100h 001001da Bank 1 through Bank 14 F00h Bank 15 F60h SFRs FFFh Data Memory Preliminary © 2008 Microchip Technology Inc. 00h 60h Valid range for ‘f’ FFh ffffffff FSR2L ffffffff ...
Page 87
... BSR. F00h F60h FFFh © 2008 Microchip Technology Inc. PIC18F2XK20/4XK20 Remapping of the Access Bank applies only to opera- tions using the Indexed Literal Offset mode. Operations that use the BSR (Access RAM bit is ‘1’) will continue to use direct addressing as before ...
Page 88
... PIC18F2XK20/4XK20 NOTES: DS41303D-page 86 Preliminary © 2008 Microchip Technology Inc. ...
Page 89
... PIC18F24K20, 32 PIC18F25K20, PIC18F44K20, PIC18F45K20 PIC18F26K20, 64 PIC18F46K20 Writing or erasing program memory will cease instruction fetches until the operation is complete. The program memory cannot be accessed during the write or erase, therefore, code cannot execute. An internal programming timer terminates program memory writes and erases. FIGURE 6-1: ...
Page 90
... Then WR bit is cleared by hardware at the completion of the write operation. Note: The EEIF interrupt flag bit of the PIR2 register is set when the write is complete. The EEIF flag stays set until cleared by firmware. Preliminary Table Latch (8-bit) TABLAT © 2008 Microchip Technology Inc. ...
Page 91
... RD bit cannot be set when EEPGD = 1 or CFGS = 1 Does not initiate an EEPROM read Note 1: When a WRERR occurs, the EEPGD and CFGS bits are not cleared. This allows tracing of the error condition. © 2008 Microchip Technology Inc. PIC18F2XK20/4XK20 R/W-0 R/W-x R/W-0 ...
Page 92
... TBLPTR based on Flash program memory operations. Operation on Table Pointer TBLPTR is not modified TBLPTR is incremented after the read/write TBLPTR is decremented after the read/write TBLPTR is incremented before the read/write TBLPTRH 8 7 (1) TABLE READ – TBLPTR<21:0> Preliminary TBLPTRL 0 TABLE WRITE (1) TBLPTR<n:0> © 2008 Microchip Technology Inc. ...
Page 93
... TBLRD*+ MOVFW TABLAT, W MOVF WORD_ODD © 2008 Microchip Technology Inc. PIC18F2XK20/4XK20 The internal program memory is typically organized by words. The Least Significant bit of the address selects between the high and low bytes of the word. Figure 6-4 shows the interface between the internal program memory and the TABLAT ...
Page 94
... TBLPTR with the base ; address of the memory block ; point to Flash program memory ; access Flash program memory ; enable write to memory ; enable block Erase operation ; disable interrupts ; write 55h ; write 0AAh ; start erase (CPU stall) ; re-enable interrupts Preliminary © 2008 Microchip Technology Inc. ...
Page 95
... EEPGD bit to point to program memory; • clear the CFGS bit to access program memory; • set WREN to enable byte writes. © 2008 Microchip Technology Inc. PIC18F2XK20/4XK20 The long write is necessary for programming the inter- nal Flash. Instruction execution is halted during a long write cycle ...
Page 96
... TBLWT holding register. Preliminary © 2008 Microchip Technology Inc. ...
Page 97
... C1IF PIE2 OSCFIE C1IE Legend: — = unimplemented, read as ‘0’. Shaded cells are not used during Flash/EEPROM access. © 2008 Microchip Technology Inc. PIC18F2XK20/4XK20 ; loop until holding registers are full ; point to Flash program memory ; access Flash program memory ; enable write to memory ...
Page 98
... PIC18F2XK20/4XK20 NOTES: DS41303D-page 96 Preliminary © 2008 Microchip Technology Inc. ...
Page 99
... EECON1 and EECON2. These are the same registers which control access to the program memory and are used in a similar manner for the data EEPROM. © 2008 Microchip Technology Inc. PIC18F2XK20/4XK20 The EECON1 register (Register 7-1) is the control reg- ister for data and program memory access. Control bit EEPGD determines if the access will be to program or data EEPROM memory ...
Page 100
... When a WRERR occurs, the EEPGD and CFGS bits are not cleared. This allows tracing of the error condition. DS41303D-page 98 R/W-0 R/W-x R/W-0 FREE WRERR WREN U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) Preliminary R/S-0 R/S bit Bit is unknown © 2008 Microchip Technology Inc. ...
Page 101
... BSF EECON1, WR BSF INTCON, GIE BCF EECON1, WREN © 2008 Microchip Technology Inc. PIC18F2XK20/4XK20 Additionally, the WREN bit in EECON1 must be set to enable writes. This mechanism prevents accidental writes to data EEPROM due to unexpected code execution (i.e., runaway programs). The WREN bit should be kept clear at all times, except when updating the EEPROM ...
Page 102
... Set for Data EEPROM ; Disable interrupts ; Enable writes ; Loop to refresh array ; Read current address ; ; Write 55h ; ; Write 0AAh ; Set WR bit to begin write ; Wait for write to complete ; Increment address ; Not zero again ; Disable writes ; Enable interrupts Preliminary © 2008 Microchip Technology Inc. ...
Page 103
... IPR2 OSCFIP C1IP PIR2 OSCFIF C1IF PIE2 OSCFIE C1IE Legend: — = unimplemented, read as ‘0’. Shaded cells are not used during Flash/EEPROM access. Note 1: PIC18F26K20/PIC18F46K20 only. © 2008 Microchip Technology Inc. PIC18F2XK20/4XK20 Bit 5 Bit 4 Bit 3 Bit 2 TMR0IE INT0IE RBIE TMR0IF EEADR5 EEADR4 EEADR3 EEADR2 EEADR1 EEADR0 — ...
Page 104
... PIC18F2XK20/4XK20 NOTES: DS41303D-page 102 Preliminary © 2008 Microchip Technology Inc. ...
Page 105
... Without hardware multiply unsigned Hardware multiply Without hardware multiply signed Hardware multiply Without hardware multiply unsigned Hardware multiply Without hardware multiply signed Hardware multiply © 2008 Microchip Technology Inc. PIC18F2XK20/4XK20 EXAMPLE 8- UNSIGNED MULTIPLY ROUTINE MOVF ARG1 MULWF ARG2 ; ARG1 * ARG2 -> ; PRODH:PRODL ...
Page 106
... PRODL RES1 Add cross PRODH products ; WREG ; ; ARG1H ARG2L ; ARG1H * ARG2L -> ; PRODH:PRODL PRODL RES1 Add cross PRODH products ; WREG ; ; ARG2H ARG2H:ARG2L neg? SIGN_ARG1 ; no, check ARG1 ARG1L RES2 ; ARG1H ARG1H ARG1H:ARG1L neg? CONT_CODE ; no, done ARG2L RES2 ; ARG2H © 2008 Microchip Technology Inc. ...
Page 107
... All interrupts branch to address 0008h in Compatibility mode. © 2008 Microchip Technology Inc. PIC18F2XK20/4XK20 9.2 Interrupt Priority The interrupt priority feature is enabled by setting the IPEN bit of the RCON register ...
Page 108
... INT2IE INT2IP IPEN IPEN GIEL/PEIE IPEN TMR0IF TMR0IE TMR0IP (1) RBIF RBIE RBIP INT1IF INT1IE INT1IP INT2IF INT2IE INT2IP Preliminary © 2008 Microchip Technology Inc. Wake- Idle or Sleep modes Interrupt to CPU Vector to Location 0008h GIEH/GIE Interrupt to CPU Vector to Location 0018h GIEH/GIE GIEL/PEIE ...
Page 109
... A mismatch condition will continue to set the RBIF bit. Reading PORTB will end the mismatch condition and allow the bit to be cleared port change interrupts also require the individual pin IOCB enables. © 2008 Microchip Technology Inc. PIC18F2XK20/4XK20 Note: Interrupt flag bits are set when an interrupt ...
Page 110
... This feature allows for software polling. DS41303D-page 108 R/W-1 U-0 R/W-1 INTEDG2 — TMR0IP U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary U-0 R/W-1 — RBIP bit Bit is unknown © 2008 Microchip Technology Inc. ...
Page 111
... User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. This feature allows for software polling. © 2008 Microchip Technology Inc. PIC18F2XK20/4XK20 R/W-0 R/W-0 U-0 INT2IE INT1IE — ...
Page 112
... R-0 R/W-0 R/W-0 TXIF SSPIF CCP1IF U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) Preliminary © 2008 Microchip Technology Inc. R/W-0 R/W-0 TMR2IF TMR1IF bit Bit is unknown ...
Page 113
... A TMR1 register capture occurred (must be cleared by software TMR1 register capture occurred Compare mode TMR1 register compare match occurred (must be cleared by software TMR1 register compare match occurred PWM mode: Unused in this mode. © 2008 Microchip Technology Inc. PIC18F2XK20/4XK20 R/W-0 R/W-0 R/W-0 EEIF BCLIF HLVDIF U = Unimplemented bit, read as ‘ ...
Page 114
... The PSPIE bit is unimplemented on 28-pin devices and will read as ‘0’. DS41303D-page 112 R/W-0 R/W-0 R/W-0 TXIE SSPIE CCP1IE U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) Preliminary R/W-0 R/W-0 TMR2IE TMR1IE bit Bit is unknown © 2008 Microchip Technology Inc. ...
Page 115
... Enabled 0 = Disabled bit 1 TMR3IE: TMR3 Overflow Interrupt Enable bit 1 = Enabled 0 = Disabled bit 0 CCP2IE: CCP2 Interrupt Enable bit 1 = Enabled 0 = Disabled © 2008 Microchip Technology Inc. PIC18F2XK20/4XK20 R/W-0 R/W-0 R/W-0 EEIE BCLIE HLVDIE U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary ...
Page 116
... Note 1: The PSPIF bit is unimplemented on 28-pin devices and will read as ‘0’. DS41303D-page 114 R/W-1 R/W-1 R/W-1 TXIP SSPIP CCP1IP U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) Preliminary R/W-1 R/W-1 TMR2IP TMR1IP bit Bit is unknown © 2008 Microchip Technology Inc. ...
Page 117
... Low priority bit 1 TMR3IP: TMR3 Overflow Interrupt Priority bit 1 = High priority 0 = Low priority bit 0 CCP2IP: CCP2 Interrupt Priority bit 1 = High priority 0 = Low priority © 2008 Microchip Technology Inc. PIC18F2XK20/4XK20 R/W-1 R/W-1 R/W-1 EEIP BCLIP HLVDIP U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared ...
Page 118
... Note 1: Actual Reset values are determined by device configuration and the nature of the device Reset. See Register 4-1 for additional information. DS41303D-page 116 R/W-1 R-1 R Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) Preliminary R/W-0 R/W-0 (1) POR BOR bit Bit is unknown © 2008 Microchip Technology Inc. ...
Page 119
... MOVFF BSR_TEMP, BSR MOVF W_TEMP, W MOVFF STATUS_TEMP, STATUS © 2008 Microchip Technology Inc. PIC18F2XK20/4XK20 9.10 TMR0 Interrupt In 8-bit mode (which is the default), an overflow in the TMR0 register (FFh → 00h) will set flag bit, TMR0IF. In 16-bit mode, an overflow in the TMR0H:TMR0L regis- ter pair (FFFFh → 0000h) will set TMR0IF. The interrupt can be enabled/disabled by setting/clearing enable bit, TMR0IE of the INTCON register ...
Page 120
... PIC18F2XK20/4XK20 NOTES: DS41303D-page 118 Preliminary © 2008 Microchip Technology Inc. ...
Page 121
... TRISA bit (= 0) will make the corresponding PORTA pin an output (i.e., enable the output driver and put the contents of the output latch on the selected pin). © 2008 Microchip Technology Inc. PIC18F2XK20/4XK20 Reading the PORTA register reads the status of the pins, whereas writing to it, will write to the PORT latch. ...
Page 122
... LATA<6> data output. Enabled in RCIO, INTIO2 and ECIO modes only. I TTL PORTA<6> data input. Enabled in RCIO, INTIO2 and ECIO modes only. O ANA Main oscillator feedback output connection (XT, HS and LP modes). O DIG System cycle clock output (F modes. Preliminary Description /4) in RC, INTIO1 and EC Oscillator OSC © 2008 Microchip Technology Inc. ...
Page 123
... Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by PORTA. Note 1: RA<7:6> and their associated latch and data direction bits are enabled as I/O pins based on oscillator configuration; otherwise, they are read as ‘0’. 2: Not implemented on PIC18F2XK20 devices. © 2008 Microchip Technology Inc. PIC18F2XK20/4XK20 I/O I/O Type O DIG LATA< ...
Page 124
... ALTERNATE CCP2 OPTION RB3 can be configured as the alternate peripheral pin for the CCP2 module by clearing the CCP2MX Config- uration bit of CONFIG3H. The default state of the CCP2MX Configuration bit is ‘1’ which selects RC1 as the CCP2 peripheral pin. Preliminary © 2008 Microchip Technology Inc. ...
Page 125
... PBADEN is set and digital inputs when PBADEN is cleared. 2: Alternate assignment for CCP2 when the CCP2MX Configuration bit is ‘0’. Default assignment is RC1. 3: All other pin functions are disabled when ICSP or ICD are enabled. © 2008 Microchip Technology Inc. PIC18F2XK20/4XK20 I/O I/O Type ...
Page 126
... RBIE TMR0IF — TMR0IP — INT2IE INT1IE — — ANS12 ANS11 ANS10 Preliminary Description (3) (3) (3) Reset Bit 1 Bit 0 Values on page RB1 RB0 WPUB1 WPUB0 60 — — 60 SLRB SLRA 61 INT0IF RBIF 57 — RBIP 57 INT2IF INT1IF 57 ANS9 ANS8 60 © 2008 Microchip Technology Inc. ...
Page 127
... The contents of the TRISC register are affected by peripheral overrides. Reading TRISC always returns the current contents, even though a peripheral device may be overriding one or more of the pins. © 2008 Microchip Technology Inc. PIC18F2XK20/4XK20 EXAMPLE 10-3: INITIALIZING PORTC CLRF PORTC ...
Page 128
... I ST PORTC<7> data input Asynchronous serial receive data input (USART module). O DIG Synchronous serial data output (USART module); takes priority over port data Synchronous serial data input (USART module). User must configure as an input. Preliminary Description © 2008 Microchip Technology Inc. ...
Page 129
... ECCP1AS ECCPASE ECCPAS2 ECCPAS1 ECCPAS0 PSSAC1 SLRCON — — Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by PORTC. Note 1: Not implemented on PIC18F2XK20 devices. © 2008 Microchip Technology Inc. PIC18F2XK20/4XK20 Bit 5 Bit 4 Bit 3 Bit 2 RC5 RC4 RC3 RC2 ...
Page 130
... EXAMPLE 10-4: INITIALIZING PORTD CLRF PORTD ; Initialize PORTD by ; clearing output ; data latches CLRF LATD ; Alternate method ; to clear output ; data latches MOVLW 0CFh ; Value used to ; initialize data ; direction MOVWF TRISD ; Set RD<3:0> as inputs ; RD<5:4> as outputs ; RD<7:6> as inputs Preliminary © 2008 Microchip Technology Inc. ...
Page 131
... P1D 0 Legend: DIG = Digital level output; TTL = TTL input buffer Schmitt Trigger input buffer Don’t care (TRIS bit does not affect port direction or is overridden for this option). © 2008 Microchip Technology Inc. PIC18F2XK20/4XK20 I/O I/O Type O DIG LATD<0> data output. ...
Page 132
... DS41303D-page 130 Bit 5 Bit 4 Bit 3 Bit 2 RD5 RD4 RD3 RD2 IBOV PSPMODE — TRISE2 DC1B1 DC1B0 CCP1M3 CCP1M2 (1) (1) — SLRE SLRD SLRC Preliminary Reset Bit 1 Bit 0 Values on page RD1 RD0 TRISE1 TRISE0 60 CCP1M1 CCP1M0 59 SLRB SLRA 61 © 2008 Microchip Technology Inc. ...
Page 133
... The Data Latch register (LATE) is also memory mapped. Read-modify-write operations on the LATE register, read and write the latched output value for PORTE. © 2008 Microchip Technology Inc. PIC18F2XK20/4XK20 The fourth pin of PORTE (MCLR/V only pin. Its operation is controlled by the MCLRE Configuration bit. When selected as a port pin (MCLRE = 0), it functions as a digital input only pin ...
Page 134
... TRISE1: RE1 Direction Control bit 1 = Input 0 = Output bit 0 TRISE0: RE0 Direction Control bit 1 = Input 0 = Output DS41303D-page 132 R/W-0 U-0 R/W-1 PSPMODE — TRISE2 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary R/W-1 R/W-1 TRISE1 TRISE0 bit Bit is unknown © 2008 Microchip Technology Inc. ...
Page 135
... Implemented only when Master Clear functionality is disabled (MCLRE Configuration bit = 0). 2: RE3 is the only PORTE bit implemented on both PIC18F2XK20 and PIC18F4XK20 devices. All other bits are implemented only when PORTE is implemented (i.e., PIC18F4XK20 devices). 3: Unimplemented on PIC18F2XK20 devices. © 2008 Microchip Technology Inc. PIC18F2XK20/4XK20 I/O I/O Type O DIG LATE< ...
Page 136
... This can cause unexpected behavior when performing read- modify-write operations on the affected port. R/W-1 R/W-1 (1) ANS4 ANS3 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) (1) (1) Preliminary R/W-1 R/W-1 R/W-1 ANS2 ANS1 ANS0 bit Bit is unknown © 2008 Microchip Technology Inc. ...
Page 137
... ANS8: RB2 Analog Select Control bit 1 = Digital input buffer of RB2 is disabled 0 = Digital input buffer of RB2 is enabled Note 1: Default state is determined by the PBADEN bit of CONFIG3H. The default state is ‘0’ When PBADEN = ‘0’. © 2008 Microchip Technology Inc. PIC18F2XK20/4XK20 (1) (1) (1) R/W-1 ...
Page 138
... The slew rate of RA6 defaults to standard rate when the pin is used as CLKOUT. DS41303D-page 136 R/W-1 R/W-1 R/W-1 (1) (1) SLRE SLRD SLRC U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) (1) (2) Preliminary R/W-1 R/W-1 SLRB SLRA bit Bit is unknown © 2008 Microchip Technology Inc. ...
Page 139
... PSP; when this happens, the IBF and OBF bits can be polled and the appropriate action taken. © 2008 Microchip Technology Inc. PIC18F2XK20/4XK20 The timing for the control signals in Write and Read modes is shown in Figure 10-3 and Figure 10-4, respectively ...
Page 140
... PIC18F2XK20/4XK20 FIGURE 10-3: PARALLEL SLAVE PORT WRITE WAVEFORMS PORTD<7:0> IBF OBF PSPIF FIGURE 10-4: PARALLEL SLAVE PORT READ WAVEFORMS PORTD<7:0> IBF OBF PSPIF DS41303D-page 138 Preliminary © 2008 Microchip Technology Inc. ...
Page 141
... PSPIP ADIP (1) (1) ANSEL ANS7 ANS6 ANS5 Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by the Parallel Slave Port. Note 1: Unimplemented on PIC18F2XK20 devices. © 2008 Microchip Technology Inc. PIC18F2XK20/4XK20 Bit 5 Bit 4 Bit 3 Bit 2 RD5 RD4 RD3 RD2 — ...
Page 142
... PIC18F2XK20/4XK20 NOTES: DS41303D-page 140 Preliminary © 2008 Microchip Technology Inc. ...
Page 143
... CCP2 pin reflects I/O state) 1011 = Compare mode: trigger special event, reset timer, start A/D conversion on CCP2 match (CCP2IF bit is set) 11xx = PWM mode © 2008 Microchip Technology Inc. PIC18F2XK20/4XK20 The Capture and Compare operations described in this chapter apply to both standard and enhanced CCP modules ...
Page 144
... Changing the pin assignment of CCP2 does not automatically change any requirements for configuring the port pin. Users must always verify that the appropriate TRIS register is configured correctly for CCP2 operation, regardless of where it is located. Interaction Preliminary © 2008 Microchip Technology Inc. ...
Page 145
... Example 11-1 shows the recommended method for switching between capture prescalers. This example also clears the prescaler counter and will not generate the “false” interrupt. © 2008 Microchip Technology Inc. PIC18F2XK20/4XK20 EXAMPLE 11-1: CHANGING BETWEEN CAPTURE PRESCALERS ...
Page 146
... T3CCP2 and Edge Detect T3CCP2 4 Set CCP2IF 4 4 T3CCP1 T3CCP2 and Edge Detect T3CCP2 T3CCP1 Preliminary TMR3H TMR3L TMR3 Enable CCPR1H CCPR1L TMR1 Enable TMR1H TMR1L TMR3H TMR3L TMR3 Enable CCPR2H CCPR2L TMR1 Enable TMR1H TMR1L © 2008 Microchip Technology Inc. ...
Page 147
... TMR3H TMR3L T3CCP1 Comparator CCPR2H CCPR2L © 2008 Microchip Technology Inc. PIC18F2XK20/4XK20 11.3.2 TIMER1/TIMER3 MODE SELECTION Timer1 and/or Timer3 must be running in Timer mode or Synchronized Counter mode if the CCP module is using the compare feature. In Asynchronous Counter mode, the compare operation will not work reliably. ...
Page 148
... CCP1M2 CCP1M1 CCP1M0 DC2B1 DC2B0 CCP2M3 CCP2M2 CCP2M1 CCP2M0 Preliminary Reset Bit 1 Bit 0 Values on page INT0IF RBIF 57 PD POR BOR 56 TMR2IF TMR1IF 60 TMR2IE TMR1IE 60 TMR2IP TMR1IP 60 TMR3IF CCP2IF 60 TMR3IE CCP2IE 60 TMR3IP CCP2IP TMR1CS TMR1ON TMR3CS TMR3ON © 2008 Microchip Technology Inc. ...
Page 149
... In PWM mode, CCPRxH is a read-only register. © 2008 Microchip Technology Inc. PIC18F2XK20/4XK20 The PWM output (Figure 11-4) has a time base (period) and a time that the output stays high (duty cycle). ...
Page 150
... When the 10-bit time base matches the CCPR 2-bit latch, then the CCPx pin is cleared (see Figure 11-3). Preliminary L register and x H until after the period PULSE WIDTH • CCPRxL:DCxB<1:0> • T (TMR2 Prescale Value) OSC DUTY CYCLE RATIO ( ) CCPRxL:DCxB<1:0> = ---------------------------------------------------------- - ( ) 4 PR2 + bits of OSC H and x © 2008 Microchip Technology Inc. ...
Page 151
... PWM Frequency 1.22 kHz Timer Prescale (1, 4, 16) 16 PR2 Value 0x65 Maximum Resolution (bits) 8 © 2008 Microchip Technology Inc. PIC18F2XK20/4XK20 EQUATION 11-4: Resolution Note: If the pulse width value is greater than the period the assigned PWM pin(s) will remain unchanged. 9.77 kHz 39 ...
Page 152
... T2CON register. 7. Enable PWM output after a new PWM cycle has started: • Wait until Timer2 overflows (TMR2IF bit of the PIR1 register is set). • Enable the CCPx pin output driver by clearing the associated TRIS bit. Preliminary © 2008 Microchip Technology Inc. ...
Page 153
... ECCP1AS ECCPASE ECCPAS2 ECCPAS1 ECCPAS0 PWM1CON PRSEN PDC6 Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by PWM or Timer2. Note 1: Not implemented on PIC18F2XK20 devices. © 2008 Microchip Technology Inc. PIC18F2XK20/4XK20 Bit 5 Bit 4 Bit 3 TMR0IE INT0IE RBIE TMR0IF — ...
Page 154
... PIC18F2XK20/4XK20 NOTES: DS41303D-page 152 Preliminary © 2008 Microchip Technology Inc. ...
Page 155
... Microchip Technology Inc. PIC18F2XK20/4XK20 The T0CON register (Register 12-1) controls all aspects of the module’s operation, including the prescale selection both readable and writable. ...
Page 156
... Timer0 is updated with the contents of TMR0H when a write occurs to TMR0L. This allows all 16 bits of Timer0 to be updated at once. ). OSC 0 Sync with Internal Clocks Programmable 1 Prescaler (2 T Delay Preliminary Set TMR0IF TMR0L on Overflow 8 8 Internal Data Bus © 2008 Microchip Technology Inc. ...
Page 157
... RA6 Legend: Shaded cells are not used by Timer0. Note 1: PORTA<7:6> and their direction bits are individually configured as port pins based on various primary oscillator modes. When disabled, these bits read as ‘0’. © 2008 Microchip Technology Inc. PIC18F2XK20/4XK20 0 Sync with Internal TMR0L ...
Page 158
... PIC18F2XK20/4XK20 NOTES: DS41303D-page 156 Preliminary © 2008 Microchip Technology Inc. ...
Page 159
... OSC bit 0 TMR1ON: Timer1 On bit 1 = Enables Timer1 0 = Stops Timer1 © 2008 Microchip Technology Inc. PIC18F2XK20/4XK20 A simplified block diagram of the Timer1 module is shown in Figure 13-1. A block diagram of the module’s operation in Read/Write mode is shown in Figure 13-2. The module incorporates its own low-power oscillator to provide an additional clocking option ...
Page 160
... RC1/T1OSI and 1 Synchronize 0 Detect Sleep Input Timer1 On/Off Set TMR1 TMR1IF High Byte on Overflow 1 Synchronize 0 Detect Sleep Input Timer1 On/Off Set TMR1 TMR1IF High Byte on Overflow 8 Read TMR1L Write TMR1L 8 TMR1H 8 8 Internal Data Bus © 2008 Microchip Technology Inc. ...
Page 161
... T1CKI = 0 when TMR1 Enabled Note 1: Arrows indicate counter increments Counter mode, a falling edge must be registered by the counter prior to the first incrementing rising edge of the clock. © 2008 Microchip Technology Inc. PIC18F2XK20/4XK20 13.2.3 READING AND WRITING TIMER1 IN ASYNCHRONOUS COUNTER MODE Reading TMR1H or TMR1L while the timer is running from an external asynchronous clock will ensure a valid read (taken care of in hardware) ...
Page 162
... Timer1 oscillator fails while providing the clock, polling the T1RUN bit will indicate whether the clock is being provided by the Timer1 oscillator or another source. ® MCU Preliminary CAPACITOR SELECTION FOR THE TIMER OSCILLATOR Freq C1 C2 (1) (1) 32 kHz © 2008 Microchip Technology Inc. ...
Page 163
... SS OSC1 OSC2 RC0 RC1 RC2 Note: Not drawn to scale. © 2008 Microchip Technology Inc. PIC18F2XK20/4XK20 13.7 Timer1 Interrupt The TMR1 register pair (TMR1H:TMR1L) increments from 0000h to FFFFh and rolls over to 0000h. The Timer1 interrupt, if enabled, is generated on overflow, which is latched in the TMR1IF interrupt flag bit of the PIR1 register ...
Page 164
... Initialize timekeeping registers ; ; Enable Timer1 interrupt ; Preload for 1 sec overflow ; Clear interrupt flag ; Increment seconds ; 60 seconds elapsed? ; No, done ; Clear seconds ; Increment minutes ; 60 minutes elapsed? ; No, done ; clear minutes ; Increment hours ; 24 hours elapsed? ; No, done ; Reset hours ; Done Preliminary © 2008 Microchip Technology Inc. ...
Page 165
... Timer1 Register, High Byte T1CON RD16 T1RUN T1CKPS1 T1CKPS0 T1OSCEN T1SYNC Legend: Shaded cells are not used by the Timer1 module. Note 1: These bits are unimplemented on 28-pin devices; always maintain these bits clear. © 2008 Microchip Technology Inc. PIC18F2XK20/4XK20 Bit 5 Bit 4 Bit 3 Bit 2 INT0IE RBIE ...
Page 166
... PIC18F2XK20/4XK20 NOTES: DS41303D-page 164 Preliminary © 2008 Microchip Technology Inc. ...
Page 167
... TMR2ON: Timer2 On bit 1 = Timer2 Timer2 is off bit 1-0 T2CKPS<1:0>: Timer2 Clock Prescale Select bits 00 = Prescaler Prescaler Prescaler is 16 © 2008 Microchip Technology Inc. PIC18F2XK20/4XK20 14.1 Timer2 Operation In normal operation, TMR2 is incremented from 00h on each clock (F /4). A 4-bit counter/prescaler on the OSC clock input gives direct input, divide-by-4 and divide-by-16 prescale options ...
Page 168
... Bit 4 Bit 3 Bit 2 INT0IE RBIE TMR0IF TXIF SSPIF CCP1IF TXIE SSPIE CCP1IE TXIP SSPIP CCP1IP Preliminary Set TMR2IF TMR2 Output (to PWM or MSSP) PR2 8 Reset Bit 1 Bit 0 Values on page INT0IF RBIF 57 TMR2IF TMR1IF 60 TMR2IE TMR1IE 60 TMR2IP TMR1IP © 2008 Microchip Technology Inc. ...
Page 169
... OSC bit 0 TMR3ON: Timer3 On bit 1 = Enables Timer3 0 = Stops Timer3 © 2008 Microchip Technology Inc. PIC18F2XK20/4XK20 A simplified block diagram of the Timer3 module is shown in Figure 15-1. A block diagram of the module’s operation in Read/Write mode is shown in Figure 15-2. The Timer3 module is controlled through the T3CON register (Register 15-1) ...
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... TRISC<1:0> are ignored and the pins are read as ‘0’. Timer1 Clock Input 1 Prescaler F /4 OSC Internal 0 Clock 2 TMR3CS Clear TMR3 TMR3L Preliminary /4). When the bit is set, Timer3 OSC 1 Synchronize Detect 0 Sleep Input Timer3 On/Off Set TMR3 TMR3IF High Byte on Overflow © 2008 Microchip Technology Inc. ...
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... The high byte of Timer3 is not directly readable or writable in this mode. All reads and writes must take place through the Timer3 High Byte Buffer register. Writes to TMR3H do not clear the Timer3 prescaler. The prescaler is only cleared on writes to TMR3L. © 2008 Microchip Technology Inc. PIC18F2XK20/4XK20 Timer1 Clock Input 1 Prescaler ...
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... Bit 3 Bit 2 INT0IE RBIE TMR0IF C2IF EEIF BCLIF HLVDIF C2IE EEIE BCLIE HLVDIE C2IP EEIP BCLIP HLVDIP T3SYNC Preliminary Reset Bit 1 Bit 0 Values on page INT0IF RBIF 57 TMR3IF CCP2IF 60 TMR3IE CCP2IE 60 TMR3IP CCP2IP TMR1CS TMR1ON 58 TMR3CS TMR3ON 59 © 2008 Microchip Technology Inc. ...
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... PWM mode; P1A, P1C active-high; P1B, P1D active-low 1110 = PWM mode; P1A, P1C active-low; P1B, P1D active-high 1111 = PWM mode; P1A, P1C active-low; P1B, P1D active-low © 2008 Microchip Technology Inc. PIC18F2XK20/4XK20 The enhanced features are discussed in detail in Section 16.4 “PWM (Enhanced Mode)”. Capture, ...
Page 174
... When configured in Single Output mode, the ECCP module functions identically to the standard CCP module in PWM mode, as described in Section 11.4 “PWM Mode”. This is also sometimes referred to as “Single CCP” mode Table 16-1. and Timer “Compare Preliminary © 2008 Microchip Technology Inc. ...
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... Full-Bridge, Reverse 11 Note 1: Outputs are enabled by pulse steering in Single mode. See Register 16-4. © 2008 Microchip Technology Inc. PIC18F2XK20/4XK20 The PWM outputs are multiplexed with I/O pins and are designated P1A, P1B, P1C and P1D. The polarity of the PWM pins is configurable and is selected by setting the CCP1M bits in the CCP1CON register appropriately ...
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... Pulse Width = T * (CCPR1L<7:0>:CCP1CON<5:4>) * (TMR2 Prescale Value) OSC • Delay = (PWM1CON<6:0>) OSC Note 1: Dead-band delay is programmed using the PWM1CON register (Section 16.4.6 “Programmable Dead-Band Delay mode”). DS41303D-page 174 Pulse 0 Width Period (1) (1) Delay Delay Preliminary © 2008 Microchip Technology Inc. PR2+1 ...
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... OSC • Pulse Width = T * (CCPR1L<7:0>:CCP1CON<5:4>) * (TMR2 Prescale Value) OSC • Delay = (PWM1CON<6:0>) OSC Note 1: Dead-band delay is programmed using the PWM1CON register (Section 16.4.6 “Programmable Dead-Band Delay mode”). © 2008 Microchip Technology Inc. PIC18F2XK20/4XK20 Pulse 0 Width Period (1) (1) Delay Delay ...
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... Note 1: At this time, the TMR2 register is equal to the PR2 register. 2: Output signals are shown as active-high. FET Driver P1A Load FET Driver P1B V+ FET Driver Load FET Driver Preliminary EXAMPLE OF HALF-BRIDGE PWM OUTPUT Period td (1) ( FET Driver FET Driver © 2008 Microchip Technology Inc. ...
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... P1A, P1B, P1C and P1D outputs are multiplexed with the PORT data latches. The associated TRIS bits must be cleared to configure the P1A, P1B, P1C and P1D pins as outputs. FIGURE 16-6: EXAMPLE OF FULL-BRIDGE APPLICATION P1A P1B P1C P1D © 2008 Microchip Technology Inc. PIC18F2XK20/4XK20 V+ QA FET Driver Load FET Driver QB ...
Page 180
... Forward Mode (2) P1A Pulse Width (2) P1B (2) P1C (2) P1D (1) Reverse Mode Pulse Width (2) P1A (2) P1B (2) P1C (2) P1D (1) Note 1: At this time, the TMR2 register is equal to the PR2 register. 2: Output signal is shown as active-high. DS41303D-page 178 Period (1) Period (1) Preliminary © 2008 Microchip Technology Inc. ...
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... When changing directions, the P1A and P1C signals switch before the end of the current PWM cycle. The modulated P1B and P1D signals are inactive at this time. The length of this time is (1/F value. © 2008 Microchip Technology Inc. PIC18F2XK20/4XK20 The Full-Bridge mode does not provide dead-band delay ...
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... PWM cycle before enabling the PWM pin output drivers. The completion of a full PWM cycle is indicated by the TMR2IF bit of the PIR1 register being set as the second PWM period begins. DS41303D-page 180 Forward Period Reverse Period Preliminary PW OFF – T OFF ON © 2008 Microchip Technology Inc. ...
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... PSSBDn: Pins P1B and P1D Shutdown State Control bits 00 = Drive pins P1B and P1D to ‘0’ Drive pins P1B and P1D to ‘1’ Pins P1B and P1D tri-state © 2008 Microchip Technology Inc. PIC18F2XK20/4XK20 A shutdown condition is indicated by the ECCPASE (Auto-Shutdown Event Status) bit of the ECCP1AS register. If the bit is a ‘ ...
Page 184
... Activity Start of PWM Period DS41303D-page 182 is a condition PWM Period Normal PWM Shutdown Shutdown Event Occurs Event Clears PWM Period Normal PWM Shutdown Shutdown Event Occurs Event Clears Preliminary ECCPASE Cleared by Firmware PWM Resumes PWM Resumes © 2008 Microchip Technology Inc. ...
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... The lower seven bits of the associated PWM1CON register (Register 16-3) sets the delay period in terms of microcontroller instruction cycles ( OSC FIGURE 16-13: EXAMPLE OF HALF-BRIDGE APPLICATIONS Standard Half-Bridge Circuit (“Push-Pull”) © 2008 Microchip Technology Inc. PIC18F2XK20/4XK20 FIGURE 16-12: Period Pulse Width (2) P1A td (2) P1B (1) ...
Page 186
... DS41303D-page 184 R/W-0 R/W-0 PDC4 PDC3 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared / cycles between the scheduled time when a PWM signal OSC OSC Preliminary R/W-0 R/W-0 R/W-0 PDC2 PDC1 PDC0 bit Bit is unknown © 2008 Microchip Technology Inc. ...
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... P1A pin is assigned to port pin Note 1: The PWM Steering mode is available only when the CCP1CON register bits CCP1M<3:2> and P1M<1:0> = 00. © 2008 Microchip Technology Inc. PIC18F2XK20/4XK20 Note: The associated TRIS bits must be set to output (‘0’) to enable the pin output driver in order to see the PWM signal on the pin. While the PWM Steering mode is active, CCP1M< ...
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... Note 1: Port outputs are configured as shown when the CCP1CON register bits P1M<1:0> and CCP1M<3:2> = 11. 2: Single PWM output requires setting at least one of the STRx bits. DS41303D-page 186 P1A pin P1B pin P1C pin P1D pin Preliminary © 2008 Microchip Technology Inc. ...
Page 189
... PORT Data FIGURE 16-16: EXAMPLE OF STEERING EVENT AT BEGINNING OF INSTRUCTION (STRSYNC = 1) PWM STRn P1<D:A> PORT Data © 2008 Microchip Technology Inc. PIC18F2XK20/4XK20 Figures 16-15 and 16-16 illustrate the timing diagrams of the PWM steering depending on the STRSYNC setting. PORT Data P1n = PWM P1n = PWM ...
Page 190
... Both Power-on Reset and subsequent Resets will force all ports to Input mode and the CCP registers to their Reset states. This forces the enhanced CCP module to reset to a state compatible with the standard CCP module. DS41303D-page 188 Preliminary © 2008 Microchip Technology Inc. ...
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... Capture/Compare/PWM Register 1, High Byte CCP1CON P1M1 P1M0 ECCP1AS ECCPASE ECCPAS2 PWM1CON PRSEN PDC6 Legend: — = unimplemented, read as ‘0’. Shaded cells are not used during ECCP operation. © 2008 Microchip Technology Inc. PIC18F2XK20/4XK20 Bit 5 Bit 4 Bit 3 TMR0IE INT0IE RBIE TMR0IF — RI ...
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... PIC18F2XK20/4XK20 NOTES: DS41303D-page 190 Preliminary © 2008 Microchip Technology Inc. ...
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... MSSP module is operated in SPI mode. Additional details are provided under the individual sections. © 2008 Microchip Technology Inc. PIC18F2XK20/4XK20 17.3 SPI Mode The SPI mode allows 8 bits of data to be synchronously transmitted and received simultaneously. All four ...
Page 194
... SSPIF interrupt is set. During transmission, double-buffered. A write to SSPBUF will write to both SSPBUF and SSPSR. R-0 R Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) Preliminary the SSPBUF is not R-0 R bit Bit is unknown © 2008 Microchip Technology Inc. ...
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... In Master mode, the overflow bit is not set since each new reception (and transmission) is initiated by writing to the SSPBUF register. 2: When enabled, these pins must be properly configured as input or output. 3: Bit combinations not specifically listed here are either reserved or implemented in I © 2008 Microchip Technology Inc. PIC18F2XK20/4XK20 R/W-0 R/W-0 R/W-0 CKP ...
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... Example 17-1 shows the loading of the SSPBUF (SSPSR) for data transmission. The SSPSR is not directly readable or writable and can only be accessed by addressing the SSPBUF register. Additionally, the MSSP STATUS register (SSPSTAT) indicates the various status conditions. Preliminary © 2008 Microchip Technology Inc. ...
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... Serial Input Buffer (SSPBUF) Shift Register (SSPSR) LSb MSb Processor 1 © 2008 Microchip Technology Inc. PIC18F2XK20/4XK20 17.3.4 TYPICAL CONNECTION Figure 17-2 shows a typical connection between two microcontrollers. The master controller (Processor 1) initiates the data transfer by sending the SCK signal. Data is shifted out of both shift registers on their pro- grammed clock edge and latched on the opposite edge of the clock ...
Page 198
... SMP bit. The time when the SSPBUF is loaded with the received data is shown. bit 2 bit 5 bit 4 bit 1 bit 3 bit 2 bit 5 bit 4 bit 3 bit 1 Preliminary give waveforms for SPI ) Clock Modes bit 0 bit 0 bit 0 bit 0 Next Q4 Cycle after Q2↓ © 2008 Microchip Technology Inc. ...
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... SSPIF Interrupt Flag SSPSR to SSPBUF © 2008 Microchip Technology Inc. PIC18F2XK20/4XK20 must be high. When the SS pin is low, transmission and reception are enabled and the SDO pin is driven. When the SS pin goes high, the SDO pin is no longer driven, even if in the middle of a transmitted byte and becomes a floating output ...
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... Input Sample (SMP = 0) SSPIF Interrupt Flag SSPSR to SSPBUF DS41303D-page 198 bit 6 bit 3 bit 2 bit 5 bit 4 bit 6 bit 3 bit 2 bit 5 bit 4 Preliminary ) 0 bit 1 bit 0 bit 0 Next Q4 Cycle after Q2↓ bit 1 bit 0 bit 0 Next Q4 Cycle after Q2↓ © 2008 Microchip Technology Inc. ...