PIC18F46K20-I/PT Microchip Technology, PIC18F46K20-I/PT Datasheet

IC PIC MCU FLASH 32KX16 44-TQFP

PIC18F46K20-I/PT

Manufacturer Part Number
PIC18F46K20-I/PT
Description
IC PIC MCU FLASH 32KX16 44-TQFP
Manufacturer
Microchip Technology
Series
PIC® XLP™ 18Fr

Specifications of PIC18F46K20-I/PT

Program Memory Type
FLASH
Program Memory Size
64KB (32K x 16)
Package / Case
44-TQFP, 44-VQFP
Core Processor
PIC
Core Size
8-Bit
Speed
64MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, HLVD, POR, PWM, WDT
Number Of I /o
35
Eeprom Size
1K x 8
Ram Size
3.8K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 3.6 V
Data Converters
A/D 14x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
PIC18F
Core
PIC
Data Bus Width
8 bit
Data Ram Size
3936 B
Interface Type
CCP, ECCP, EUSART, I2C, MSSP, SPI
Maximum Clock Frequency
64 MHz
Number Of Programmable I/os
36
Number Of Timers
4
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, DV164136
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 14 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
AC164112 - VOLTAGE LIMITER MPLAB ICD2 VPPDM164124 - KIT STARTER FOR PIC18F4XK20AC164305 - MODULE SKT FOR PM3 44TQFP
Lead Free Status / Rohs Status
Lead free / RoHS Compliant

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1.0
This
specifications for the following devices:
• PIC18F23K20
• PIC18F24K20
• PIC18F25K20
• PIC18F26K20
• PIC18F43K20
• PIC18F44K20
• PIC18F45K20
• PIC18F46K20
2.0
The PIC18F2XK20/4XK20 devices can be pro-
grammed using either the high-voltage In-Circuit Serial
Programming™ (ICSP™) method or the low-voltage
ICSP method. Both methods can be done with the
device in the users’ system. The low-voltage ICSP
method is slightly different than the high-voltage
method and these differences are noted where applica-
ble. This programming specification applies to the
PIC18F2XK20/4XK20 devices in all package types.
TABLE 2-1:
© 2009 Microchip Technology Inc.
MCLR/V
V
V
RB5
RB6
RB7
Legend: I = Input, O = Output, P = Power
Note 1:
DD
SS (2)
Pin Name
(2)
2:
document
DEVICE OVERVIEW
PROGRAMMING OVERVIEW
PP
See Figure 5-1 for more information.
All power supply (V
/RE3
Flash Memory Programming Specification
PIN DESCRIPTIONS (DURING PROGRAMMING): PIC18F2XK20/4XK20
Pin Name
includes
PGM
PGC
PGD
V
V
V
DD
PP
SS
DD
) and ground (V
the
Pin Type
PIC18F2XK20/4XK20
I/O
programming
P
P
P
I
I
Advance Information
SS
Programming Enable
Power Supply
Ground
Low-Voltage ICSP™ input when LVP Configuration bit equals ‘1’
Serial Clock
Serial Data
) pins must be connected.
During Programming
2.1
In High-Voltage ICSP mode, the PIC18F2XK20/4XK20
devices require two programmable power supplies:
one for V
should have a minimum resolution of 0.25V. Refer to
Section 6.0
Requirements for Program/Verify Test Mode” for
additional hardware parameters.
2.1.1
In Low-Voltage ICSP mode, the PIC18F2XK20/4XK20
devices can be programmed using a single V
in the operating range. The MCLR/V
have to be brought to a different voltage, but can
instead be left at the normal operating voltage. Refer to
Section 6.0
Requirements for Program/Verify Test Mode” for
additional hardware parameters.
2.2
The pin diagrams for the PIC18F2XK20/4XK20 family
are shown in Figure 2-3 and Figure 2-4.
DD
Hardware Requirements
Pin Diagrams
LOW-VOLTAGE ICSP
PROGRAMMING
Pin Description
and one for MCLR/V
“AC/DC
“AC/DC
Characteristics
Characteristics
PP
/RE3. Both supplies
PP
DS41297F-page 1
/RE3 does not
DD
Timing
Timing
source
(1)

PIC18F46K20-I/PT Summary of contents

Page 1

... PIC18F24K20 • PIC18F25K20 • PIC18F26K20 • PIC18F43K20 • PIC18F44K20 • PIC18F45K20 • PIC18F46K20 2.0 PROGRAMMING OVERVIEW The PIC18F2XK20/4XK20 devices can be pro- grammed using either the high-voltage In-Circuit Serial Programming™ (ICSP™) method or the low-voltage ICSP method. Both methods can be done with the device in the users’ ...

Page 2

... The following devices are included in 28-pin QFN parts: PIC18F23K20, PIC18F24K20, PIC18F25K20, PIC18F26K20. DS41297F-page 2 RB7/PGD 1 28 RB6/PGC 27 2 RB5/PGM 26 3 RB4 4 25 RB3 5 24 RB2 6 23 RB1 22 7 RB0 RC7 11 18 RC6 17 12 RC5 16 13 RC4 RB3 2 20 RB2 3 RB1 19 PIC18F2XK20 RB0 RC7 Advance Information DD SS © 2009 Microchip Technology Inc. ...

Page 3

... The following devices are included in 40-pin PDIP parts: PIC18F43K20, PIC18F44K20, PIC18F45K20, PIC18F46K20. FIGURE 2-4: 44-PIN TQFP PIN DIAGRAMS 44-PIN TQFP RC7 RD4 RD5 RD6 RD7 RB0 RB1 RB2 RB3 Note: The following devices are included in 44-pin TQFP parts: PIC18F43K20, PIC18F44K20, PIC18F45K20, PIC18F46K20. © 2009 Microchip Technology Inc. PIC18F2XK20/4XK20 ...

Page 4

... PIC18F2XK20/4XK20 FIGURE 2-5: 44-PIN QFN PIN DIAGRAMS 44-PIN QFN RC7 RD4 RD5 RD6 RD7 RB0 RB1 RB2 Note: The following devices are included in 44-pin QFN parts: PIC18F43K20, PIC18F44K20, PIC18F45K20, PIC18F46K20. DS41297F-page 4 OSC2 1 33 OSC1 PIC18F4XK20 RE2 27 7 RE1 26 8 RE0 9 25 ...

Page 5

... Code Memory 01FFFFh Unimplemented Read as ‘0’ 200000h Configuration and ID Space 3FFFFFh Note: Sizes of memory areas are not to scale. © 2009 Microchip Technology Inc. PIC18F2XK20/4XK20 TABLE 2-2: IMPLEMENTATION OF CODE MEMORY Device PIC18F23K20 PIC18F43K20 MEMORY SIZE/DEVICE 8 Kbytes (PIC18FX3K20) Boot Block Block 0 ...

Page 6

... IMPLEMENTATION OF CODE MEMORY Device PIC18F24K20 PIC18F44K20 MEMORY SIZE/DEVICE 16 Kbytes (PIC18FX4K20) Boot Block Block 0 Block 1 Unimplemented Read ‘0’s Advance Information Code Memory Size (Bytes) 000000h-003FFFh (16K) Address Range 000000h 0007FFh 000800h 001FFFh 002000h 003FFFh 004000h 01FFFFh © 2009 Microchip Technology Inc. ...

Page 7

... MEMORY MAP AND THE CODE MEMORY SPACE FOR PIC18FX5K20 DEVICES 000000h Code Memory 01FFFFh Unimplemented Read as ‘0’ 200000h Configuration and ID Space 3FFFFFh Note: Sizes of memory areas not to scale. © 2009 Microchip Technology Inc. PIC18F2XK20/4XK20 TABLE 2-4: IMPLEMENTATION OF CODE MEMORY Device PIC18F25K20 PIC18F45K20 MEMORY SIZE/DEVICE 32 Kbytes (PIC18FX5K20) Boot Block Block 0 ...

Page 8

... Configuration and ID Space 3FFFFFh Note: Sizes of memory areas not to scale. DS41297F-page 8 TABLE 2-5: IMPLEMENTATION OF CODE MEMORY through Device PIC18F26K20 PIC18F46K20 MEMORY SIZE/DEVICE 32 Kbytes (PIC18FX6K20) Boot Block Block 0 Block 1 Block 2 Block 3 Unimplemented Read ‘0’s Advance Information Code Memory Size (Bytes) 000000h-00FFFFh (64K) ...

Page 9

... Configuration and ID Space 2FFFFFh 3FFFFFh Note: Sizes of memory areas are not to scale. © 2009 Microchip Technology Inc. PIC18F2XK20/4XK20 2.3.1 MEMORY ADDRESS POINTER Memory in the address space, 0000000h to 3FFFFFh, is addressed via the Table Pointer register, which is comprised of three Pointer registers: • TBLPTRU, at RAM address 0FF8h • ...

Page 10

... FIGURE 2-12: D110 MCLR/V /RE3 PGD PGC FIGURE 2-13: MCLR/V /RE3 PP D110 V DD PGD PGC Advance Information /RE3 IHH ENTERING HIGH-VOLTAGE PROGRAM/VERIFY MODE P13 P12 P1 PGD = Input EXITING HIGH-VOLTAGE PROGRAM/VERIFY MODE P16 P17 P1 PGD = Input © 2009 Microchip Technology Inc. ...

Page 11

... PGM V IH PGD PGC PGD = Input © 2009 Microchip Technology Inc. PIC18F2XK20/4XK20 2.7 Serial Program/Verify Operation The PGC pin is used as a clock input pin and the PGD pin is used for entering command bits and data input/ output during serial operation. Commands and data are ...

Page 12

... Core Instruction Command Payload 1101 3C 40 Table Write, post-increment by 2 FIGURE 2-16: TABLE WRITE, POST-INCREMENT TIMING DIAGRAM (1101) P2 P2A P2B PGC PGD 4-bit Command DS41297F-page 16-bit Data Payload PGD = Input Advance Information P5A Fetch Next 4-bit Command © 2009 Microchip Technology Inc. ...

Page 13

... P11). During this time, PGC may continue to toggle but PGD must be held low. © 2009 Microchip Technology Inc. PIC18F2XK20/4XK20 The code sequence to erase the entire device is shown in Table 3-2 and the flowchart is shown in Figure 3-1. ...

Page 14

... Row Erase is identical to the data EEPROM write timing shown in Figure 3-7. Note: The TBLPTR register can point at any byte within the row intended for erase. Advance Information P10 P11 16-bit Erase Time Data Payload © 2009 Microchip Technology Inc. ...

Page 15

... Step 6: Repeat step 3 with Address Pointer incremented by 64 until all rows are erased. Step 7: Disable writes 0000 Note 1: See Figure 4-4 for details on shift out data timing. © 2009 Microchip Technology Inc. PIC18F2XK20/4XK20 Core Instruction BSF EECON1, EEPGD BCF EECON1, CFGS ...

Page 16

... PIC18F2XK20/4XK20 FIGURE 3-3: SINGLE ROW ERASE CODE MEMORY FLOW Addr = Addr + 64 DS41297F-page 16 Start Addr = 0 Configure Device for Row Erases Perform Erase Sequence No WR Bit Clear? Yes All No Rows done? Yes Done Advance Information © 2009 Microchip Technology Inc. ...

Page 17

... NOP is issued, where the 4th PGC is held high for the duration of the programming time, P9. TABLE 3-4: WRITE AND ERASE BUFFER SIZES Devices (Arranged by Family) PIC18F26K20, PIC18F46K20 PIC18F24K20, PIC18F25K20, PIC18F44K20, PIC18F45K20 PIC18F23K20, PIC18F43K20 TABLE 3-5: WRITE CODE MEMORY CODE SEQUENCE 4-bit ...

Page 18

... Yes Start Write Sequence and Hold PGC High until Done and Wait P9 Hold PGC Low for Time P10 All No locations done? Yes Done P5A 4-bit Command PGD = Input Advance Information P10 ( 16-bit Programming Time Data Payload © 2009 Microchip Technology Inc. ...

Page 19

... Table 3-4) at each iteration of the loop. The write cycle must be repeated enough times to completely rewrite the contents of the erase buffer. Step 8: Disable writes 0000 © 2009 Microchip Technology Inc. PIC18F2XK20/4XK20 The appropriate number of bytes required for the erase buffer must be read out of code memory (as described in Section 4.2 “Verify Code Memory and ID Loca- tions” ...

Page 20

... PROGRAM DATA FLOW Start Set Address Set Data Enable Write Start Write Sequence No WR bit clear? Yes No done? Yes Done P10 1 2 P11A n n 16-bit Data Payload (see below P5A Shift Out Data (see Figure 4-4) PGD = Output © 2009 Microchip Technology Inc. ...

Page 21

... Step 7: Hold PGC low for time P10. Step 8: Disable writes 0000 Repeat steps 2 through 8 to write more data. Note 1: See Figure 4-4 for details on shift out data timing. © 2009 Microchip Technology Inc. PIC18F2XK20/4XK20 Core Instruction BCF EECON1, EEPGD BCF EECON1, CFGS MOVLW <Addr> ...

Page 22

... Write 2 bytes and post-increment address by 2. Write 2 bytes and post-increment address by 2. Write 2 bytes and post-increment address by 2. Write 2 bytes and start programming. NOP - hold PGC high for time P9 and low for time P10. Advance Information © 2009 Microchip Technology Inc. ...

Page 23

... Address Program LSB Delay P9 and P10 Time for Write Done © 2009 Microchip Technology Inc. PIC18F2XK20/4XK20 3.6 Configuration Bits Programming Unlike code memory, the Configuration bits are programmed a byte at a time. The Table Write, Begin Programming 4-bit command (‘1111’) is used, but only 8 bits of the following 16-bit payload will be written ...

Page 24

... Core Instruction MOVLW Addr[21:16] MOVWF TBLPTRU MOVLW <Addr[15:8]> MOVWF TBLPTRH MOVLW <Addr[7:0]> MOVWF TBLPTRL TBLRD *+ P14 LSb Shift Data Out PGD = Output Advance Information P5A (Note MSb Fetch Next 4-bit Command PGD = Input © 2009 Microchip Technology Inc. ...

Page 25

... Yes All No code memory verified? Yes © 2009 Microchip Technology Inc. PIC18F2XK20/4XK20 The Table Pointer must be manually set to 200000h (base address of the ID locations) once the code memory has been verified. The post-increment feature of the table read 4-bit command can not be used to increment the Table Pointer beyond the code memory space ...

Page 26

... MOVLW <Addr> MOVWF EEADR MOVLW <AddrH> MOVWF EEADRH BSF EECON1, RD MOVF EEDATA MOVWF TABLAT NOP (1) Shift Out Data Advance Information READ DATA EEPROM FLOW Start Set Address Read Byte Move to TABLAT Shift Out Data done? Yes Done © 2009 Microchip Technology Inc. ...

Page 27

... PGD via the 4-bit command, ‘0010’ (TABLAT register). The result may then be immediately compared to the appropriate data in the programmer’s memory for verification. Refer to Section 4.4 “Read Data EEPROM Memory” for implementation details of reading data EEPROM. © 2009 Microchip Technology Inc. PIC18F2XK20/4XK20 ...

Page 28

... Value FOSC1 FOSC0 00-- 0111 ---1 1111 ---1 1111 1--- 1011 — STVREN 10-- -1-1 CP1 CP0 ---- 1111 — — 11-- ---- WRT1 WRT0 ---- 1111 — — 111- ---- EBTR1 EBTR0 ---- 1111 — — -1-- ---- REV1 REV0 See Table 5-2 DEV4 DEV3 See Table 5-2 © 2009 Microchip Technology Inc. ...

Page 29

... TABLE 5-2: DEVICE ID VALUE Device PIC18F23K20 PIC18F24K20 PIC18F25K20 PIC18F26K20 PIC18F43K20 PIC18F44K20 PIC18F45K20 PIC18F46K20 Note: The ‘x’s in DEVID1 contain the device revision code. © 2009 Microchip Technology Inc. PIC18F2XK20/4XK20 Device ID Value DEVID2 20h 20h 20h 20h 20h 20h 20h 20h Advance Information ...

Page 30

... Watchdog Timer Postscaler Select bits 1111 = 1:32,768 1110 = 1:16,384 1101 = 1:8,192 1100 = 1:4,096 1011 = 1:2,048 1010 = 1:1,024 1001 = 1:512 1000 = 1:256 0111 = 1:128 0110 = 1:64 0101 = 1:32 0100 = 1:16 0011 = 1:8 0010 = 1:4 0001 = 1:2 0000 = 1:1 Advance Information © 2009 Microchip Technology Inc. ...

Page 31

... CONFIG4L XINST CONFIG4L LVP CONFIG4L STVREN CONFIG4L . © 2009 Microchip Technology Inc. PIC18F2XK20/4XK20 Description Watchdog Timer Enable bit 1 = WDT enabled 0 = WDT disabled (control is placed on SWDTEN bit) MCLR Pin Enable bit 1 = MCLR pin enabled, RE3 input pin disabled 0 = RE3 input pin enabled, MCLR pin disabled ...

Page 32

... Data EEPROM is not write-protected 0 = Data EEPROM is write-protected Write Protection bit (Boot Block memory area Boot Block is not write-protected 0 = Boot Block is write-protected Write Protection bit (Configuration registers Configuration registers are not write-protected 0 = Configuration registers are write-protected Advance Information © 2009 Microchip Technology Inc. ...

Page 33

... DEVID2 DEV<2:0> DEVID1 REV<4:0> DEVID1 . © 2009 Microchip Technology Inc. PIC18F2XK20/4XK20 Description Table Read Protection bit (Block 3 code memory area Block 3 is not protected from table reads executed in other blocks 0 = Block 3 is protected from table reads executed in other blocks Table Read Protection bit (Block 2 code memory area) ...

Page 34

... EEPROM information may be pro- vided. When embedding data EEPROM information in . IHH the hex file, it should start at address F00000h. Microchip Technology Inc. believes that this feature is important for the benefit of the end customer. 5.6 Checksum Computation The checksum is calculated by summing the following: to the MCLR/ • ...

Page 35

... Legend: Item Description CONFIGx = Configuration Word SUM[a:b] = Sum of locations inclusive SUM_ID = Byte-wise sum of lower four bits of all customer ID locations + = Addition & = Bit-wise AND © 2009 Microchip Technology Inc. PIC18F2XK20/4XK20 Checksum Advance Information 0xAA at 0 Blank and Max Value Address E33Eh E294h ...

Page 36

... SUM[a:b] = Sum of locations inclusive SUM_ID = Byte-wise sum of lower four bits of all customer ID locations + = Addition & = Bit-wise AND DS41297F-page 36 Checksum Advance Information 0xAA at 0 Blank and Max Value Address 8362h 82B8h 8B35h 8AEAh C332h C2E7h 0326h 0330h © 2009 Microchip Technology Inc. ...

Page 37

... Legend: Item Description CONFIGx = Configuration Word SUM[a:b] = Sum of locations inclusive SUM_ID = Byte-wise sum of lower four bits of all customer ID locations + = Addition & = Bit-wise AND © 2009 Microchip Technology Inc. PIC18F2XK20/4XK20 Checksum Advance Information 0xAA at 0 Blank and Max Value Address 0362h 02B8h ...

Page 38

... T CY PWRT Advance Information Units Conditions Row Erase/Write V Bulk Erase operations μ meet AC specifications μs (Note 3.6V DD μ Externally Timed ms Configuration Word programming time μ the Power-up Timer period and © 2009 Microchip Technology Inc. ...

Page 39

... T CY PWRT + 1.5 μs (for EC mode only) where the oscillator period. For specific values, refer to the Electrical Characteristics section of the device data OSC sheet for the particular device. © 2009 Microchip Technology Inc. PIC18F2XK20/4XK20 Min. Max. /RE3 ↑ /RE3 ↑ ...

Page 40

... PIC18F2XK20/4XK20 NOTES: DS41297F-page 40 Advance Information © 2009 Microchip Technology Inc. ...

Page 41

... REAL ICE, rfLAB, Select Mode, Total Endurance, TSHARC, UniWinDriver, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. ...

Page 42

... France - Paris Tel: 33-1-69-53-63-20 Fax: 33-1-69-30-90-79 Germany - Munich Tel: 49-89-627-144-0 Fax: 49-89-627-144-44 Italy - Milan Tel: 39-0331-742611 Fax: 39-0331-466781 Netherlands - Drunen Tel: 31-416-690399 Fax: 31-416-690340 Spain - Madrid Tel: 34-91-708-08-90 Fax: 34-91-708-08- Wokingham Tel: 44-118-921-5869 Fax: 44-118-921-5820 03/26/09 © 2009 Microchip Technology Inc. ...

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