PIC18F46K20-I/PT Microchip Technology, PIC18F46K20-I/PT Datasheet - Page 27

• Manufacturer Part Number: PIC18F46K20-I/PT
• Description: IC PIC MCU FLASH 32KX16 44-TQFP
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 18Fr

Specifications of PIC18F46K20-I/PT

• Program Memory Type: FLASH
• Program Memory Size: 64KB (32K x 16)
• Package / Case: 44-TQFP, 44-VQFP
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 64MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, HLVD, POR, PWM, WDT
• Number Of I /o: 35
• Eeprom Size: 1K x 8
• Ram Size: 3.8K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 14x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 3936 B
• Interface Type: CCP, ECCP, EUSART, I2C, MSSP, SPI
• Maximum Clock Frequency: 64 MHz
• Number Of Programmable I/os: 36
• Number Of Timers: 4
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, DV164136
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 14 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC164112 - VOLTAGE LIMITER MPLAB ICD2 VPPDM164124 - KIT STARTER FOR PIC18F4XK20AC164305 - MODULE SKT FOR PM3 44TQFP
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

FIGURE 4-4:
FIGURE 4-5:
4.5
A data EEPROM address may be read via a sequence
of core instructions (4-bit command, ‘0000’) and then
output on PGD via the 4-bit command, ‘0010’ (TABLAT
register). The result may then be immediately
compared to the appropriate data in the programmer’s
memory for verification. Refer to Section 4.4 “Read
Data EEPROM Memory” for implementation details of
reading data EEPROM.
© 2009 Microchip Technology Inc.
PGC
PGD
Note 1:
PGC
PGD
Verify Data EEPROM
1
0
2
1
Magnification of the High-Impedance delay between PGC and PGD is shown in Figure 4-5.
MSb
3
0
4
0
SHIFT OUT DATA HOLDING REGISTER TIMING DIAGRAM (0010)
HIGH-IMPEDANCE DELAY
P5
PGD = Input
1
1
n
P19
2
P3
3
2
4
n
5
Advance Information
6
7
8
P6
LSb
9
P14
4.6
The term “Blank Check” means to verify that the device
has no programmed memory cells. All memories must
be verified: code memory, data EEPROM, ID locations
and Configuration bits. The device ID registers
(3FFFFEh:3FFFFFh) should be ignored.
A “blank” or “erased” memory cell will read as a ‘1’.
Therefore, Blank Checking a device merely means to
verify that all bytes read as FFh except the Configura-
tion bits. Unused (reserved) Configuration bits will read
‘0’ (programmed). Refer to Table 5-1 for blank configu-
ration expect data for the various PIC18F2XK20/
4XK20 devices.
Given that Blank Checking is merely code and data
EEPROM verification with FFh expect data, refer to
Section 4.4 “Read Data EEPROM Memory” and
Section 4.2 “Verify Code Memory and ID Locations”
for implementation details.
FIGURE 4-6:
PIC18F2XK20/4XK20
10 11
1
2
PGD = Output
12
Shift Data Out
Blank Check
3
Blank Check Device
13
4
14
device
Abort
blank?
5
Start
Is
15 16
No
6
BLANK CHECK FLOW
MSb
P5A
(Note 1)
(Note 1)
Fetch Next 4-bit Command
Yes
1
n
PGD = Input
2
n
DS41297F-page 27
3
Continue
n
4
n