ATMEGA8A-MU Atmel, ATMEGA8A-MU Datasheet - Page 150

• Manufacturer Part Number: ATMEGA8A-MU
• Description: MCU AVR 8K FLASH 16MHZ 32-QFN
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA8A-MU

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 23
• Program Memory Size: 8KB (4K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 512 x 8
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-VQFN Exposed Pad, 32-HVQFN, 32-SQFN, 32-DHVQFN
• Controller Family/series: AVR MEGA
• No. Of I/o's: 23
• Eeprom Memory Size: 512Byte
• Ram Memory Size: 1KB
• Cpu Speed: 16MHz
• No. Of Timers: 3
• Rohs Compliant: Yes
• Processor Series: ATMEGA8x
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 1 KB
• Interface Type: SPI, TWI, USART
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 23
• Number Of Timers: 3
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• For Use With: ATSTK600 - DEV KIT FOR AVR/AVR32ATSTK500 - PROGRAMMER AVR STARTER KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

19.6.11
Flushing the Receive
Buffer
19.7
19.7.1
8159D–AVR–02/11
Asynchronous Data Reception
Disabling the Receiver
Asynchronous Clock Recovery
The PE bit is set if the next character that can be read from the receive buffer had a parity error
when received and the parity checking was enabled at that point (UPM1 = 1). This bit is valid
until the receive buffer (UDR) is read.
In contrast to the Transmitter, disabling of the Receiver will be immediate. Data from ongoing
receptions will therefore be lost. When disabled (i.e., the RXEN is set to zero) the Receiver will
no longer override the normal function of the RxD port pin. The Receiver buffer FIFO will be
flushed when the Receiver is disabled. Remaining data in the buffer will be lost
The Receiver buffer FIFO will be flushed when the Receiver is disabled (i.e., the buffer will be
emptied of its contents). Unread data will be lost. If the buffer has to be flushed during normal
operation, due to for instance an error condition, read the UDR I/O location until the RXC Flag is
cleared. The following code example shows how to flush the receive buffer.
Note:
The USART includes a clock recovery and a data recovery unit for handling asynchronous data
reception. The clock recovery logic is used for synchronizing the internally generated baud rate
clock to the incoming asynchronous serial frames at the RxD pin. The data recovery logic sam-
ples and low pass filters each incoming bit, thereby improving the noise immunity of the
Receiver. The asynchronous reception operational range depends on the accuracy of the inter-
nal baud rate clock, the rate of the incoming frames, and the frame size in number of bits.
The clock recovery logic synchronizes internal clock to the incoming serial frames.
illustrates the sampling process of the start bit of an incoming frame. The sample rate is 16 times
the baud rate for Normal mode, and eight times the baud rate for Double Speed mode. The hor-
izontal arrows illustrate the synchronization variation due to the sampling process. Note the
larger time variation when using the Double Speed mode (U2X = 1) of operation. Samples
denoted zero are samples done when the RxD line is idle (i.e., no communication activity).
Assembly Code Example
C Code Example
USART_Flush:
void USART_Flush( void )
{
}
sbis UCSRA, RXC
ret
in
rjmp USART_Flush
unsigned char dummy;
while ( UCSRA & (1<<RXC) ) dummy = UDR;
1. See “About Code Examples” on page 6.
r16, UDR
(1)
(1)
ATmega8A
Figure 19-5
150