PIC24HJ12GP201-I/SO Microchip Technology, PIC24HJ12GP201-I/SO Datasheet
PIC24HJ12GP201-I/SO
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... Microchip Technology Inc. PIC24HJ12GP201/202 High-Performance, 16-bit Microcontrollers Preliminary Data Sheet DS70282D ...
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... PICDEM, PICDEM.net, PICtail, PIC Select Mode, Total Endurance, TSHARC, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. ...
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... On-Chip Flash and SRAM: • Flash program memory (12 Kbytes) • Data SRAM (1024 bytes) • Boot and General Security for Program Flash © 2009 Microchip Technology Inc. PIC24HJ12GP201/202 Digital I/O: • Peripheral Pin Select Functionality • programmable digital I/O pins • Wake-up/Interrupt-on-Change for pins • ...
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... Fully static design • 3.3V (±10%) operating voltage • Industrial and extended temperature • Low power consumption Packaging: • 18-pin SDIP/SOIC • 28-pin SDIP/SOIC/QFN/SSOP Note: See Table 1 for the exact peripheral features per device. Preliminary © 2009 Microchip Technology Inc. ...
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... PIC24HJ12GP201/202 Product Families The device names, pin counts, memory sizes and peripheral availability of each family are listed below, followed by their pinout diagrams. TABLE 1: PIC24HJ12GP201/202 CONTROLLER FAMILIES Device PIC24HJ12GP201 PIC24HJ12GP202 Note 1: Only two out of three timers are remappable. 2: Only two out of three interrupts are remappable. ...
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... CAP DDCORE 10 19 Vss (1) /CN1/RB4 TDO/SDA1/RP9 11 18 TCK/SCL1/RP8 INT0/RP7 16 (1) /CN27/RB5 ASCL1/RP6 14 15 Preliminary = Pins are tolerant /CN11/RB15 /CN12/RB14 /CN21/RB9 /CN22/RB8 /CN23/RB7 = Pins are tolerant (1) /CN11/RB15 (1) /CN12/RB14 (1) /CN13/RB13 (1) /CN14/RB12 (1) /CN15/RB11 (1) /CN16/RB10 (1) /CN21/RB9 (1) /CN22/RB8 (1) /CN23/RB7 (1) /CN24/RB6 © 2009 Microchip Technology Inc. ...
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... AN5/RP3 /CN7/RB3 OSC1/CLKI/CN30/RA2 OSC2/CLKO/CN29/RA3 Note 1: The RPn pins can be used by any remappable peripheral. See Table 1 for the list of available peripherals. 2: The metal plane at the bottom of the device is not connected to any pins and is recommended to be connected © 2009 Microchip Technology Inc. PIC24HJ12GP201/202 ...
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... When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are using. Customer Notification System Register on our web site at www.microchip.com to receive the most current information on all of our products. DS70282D-page 6 Preliminary © 2009 Microchip Technology Inc. ...
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... DEVICE OVERVIEW This data sheet summarizes the features of the PIC24HJ12GP201/202 devices not intended comprehensive reference source. To comple- ment the information in this data sheet, refer to the “PIC24H Family Reference Manual”. Please see the Microchip web site (www.microchip.com) for the lat- est family reference manual sections ...
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... FIGURE 1-1: PIC24HJ12GP201/202 BLOCK DIAGRAM PSV and Table Data Access Control Block Interrupt Controller 8 23 PCH PCL PCU 23 Program Counter Stack Control Logic 23 Address Latch Program Memory Data Latch 24 Instruction Decode and Control Control Signals to Various Blocks Power-up Timing OSC2/CLKO Timer ...
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... Legend: CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels PPS = Peripheral Pin Select © 2009 Microchip Technology Inc. PIC24HJ12GP201/202 Description Analog input channels. External clock source input. Always associated with OSC1 pin function. Oscillator crystal output. Connects to crystal or resonator in Crystal Oscillator mode ...
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... Positive supply for analog modules. This pin must be connected at all times. Master Clear (Reset) input. This pin is an active-low Reset to the device. Ground reference for analog modules. Positive supply for peripheral logic and I/O pins. Analog = Analog input O = Output Preliminary P = Power I = Input © 2009 Microchip Technology Inc. ...
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... Microchip (www.microchip.com). 2.1 Basic Connection Requirements Getting started with the PIC24HJ12GP201/202 family of 16-bit microcontrollers requires attention to a minimal set of device pin connections before proceeding with development. The following is a list of pin names, which must always be connected: • All V and V ...
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... Discharge (ESD) or Electrical Overstress (EOS). Ensure that the MCLR pin V IH for Preliminary and V ) and fast signal shown in Figure 2-2, it EXAMPLE OF MCLR PIN CONNECTIONS R R1 MCLR PIC24H JP C and V specifications are met and V specifications are met. IL © 2009 Microchip Technology Inc. is ...
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... REAL ICE™ In-Circuit Emulator User's Guide” DS51616 ® • “Using MPLAB REAL ICE™ In-Circuit Emulator” (poster) DS51749 © 2009 Microchip Technology Inc. 2.6 External Oscillator Pins Many microcontrollers have options for at least two oscillators: a high-frequency primary oscillator and a low-frequency secondary Section 8.0 “ ...
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... DS70282D-page 14 2.9 Unused I/Os Unused I/O pins should be configured as outputs and driven to a logic low state. Alternately, connect 10k resistor to V unused pins and drive the output to logic low. Preliminary © 2009 Microchip Technology Inc ...
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... The data space also includes 2 Kbytes of DMA RAM, which is primarily used for DMA data transfers, but may be used as general purpose RAM. 3.2 Special MCU Features The PIC24HJ12GP201/202 features a 17-bit by 17-bit, single-cycle multiplier. The multiplier can perform signed, unsigned and mixed-sign multiplication. Using A single-cycle ...
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... PIC24HJ12GP201/202 FIGURE 3-1: PIC24HJ12GP201/202 CPU CORE BLOCK DIAGRAM PSV and Table Data Access Control Block Interrupt Controller 8 23 PCU 23 Program Counter Stack Control Logic 23 Address Latch Program Memory Data Latch 24 Instruction Decode and Control Control Signals to Various Blocks DS70282D-page 16 X Data Bus ...
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... FIGURE 3-2: PIC24HJ12GP201/202 PROGRAMMER’S MODEL PC22 0 7 TBLPAG Data Table Page Address 7 0 PSVPAG — — — — — — SRH © 2009 Microchip Technology Inc. PIC24HJ12GP201/202 D15 D0 W0/WREG W10 W11 W12 W13 W14/Frame Pointer W15/Stack Pointer SPLIM PC0 0 Program Space Visibility Page Address ...
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... PIC24HJ12GP201/202 3.3 CPU Control Registers REGISTER 3-1: SR: CPU STATUS REGISTER U-0 U-0 U-0 — — — bit 15 (1) (2) R/W-0 R/W-0 R/W-0 (2) IPL<2:0> bit 7 Legend Clear only bit R = Readable bit S = Set only bit W = Writable bit ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-9 Unimplemented: Read as ‘ ...
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... Program space visible in data space 0 = Program space not visible in data space bit 1-0 Unimplemented: Read as ‘0’ Note 1: The IPL3 bit is concatenated with the IPL<2:0> bits (SR<7:5>) to form the CPU interrupt priority level. © 2009 Microchip Technology Inc. PIC24HJ12GP201/202 U-0 U-0 U-0 — — ...
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... PIC24HJ12GP201/202 3.4 Arithmetic Logic Unit (ALU) The PIC24HJ12GP201/202 ALU is 16 bits wide and is capable of addition, subtraction, bit shifts, and logic operations. Unless otherwise mentioned, arithmetic operations are 2’s complement in nature. Depending on the operation, the ALU may affect the values of the Carry (C), Zero (Z), Negative (N), Overflow (OV), and Digit Carry (DC) Status bits in the SR register ...
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... The exception is the use of TBLRD/TBLWT operations, which use TBLPAG<7> to permit access to the features Configuration bits and Device ID sections of the configuration memory space. The memory map for the PIC24HJ12GP201/202 family of devices is shown in Figure 4-1. PIC24HJ12GP201/202 0x000000 GOTO Instruction 0x000002 Reset Address ...
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... A GOTO instruction is programmed by the user application at 0x000000, with the actual address for the start of code at 0x000002. PIC24HJ12GP201/202 devices also have two interrupt vector tables, located from 0x000004 to 0x0000FF and 0x000100 to 0x0001FF. These vector tables allow each of the many device interrupt sources to be handled by separate Interrupt Service Routines (ISRs) ...
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... Data Address Space The PIC24HJ12GP201/202 CPU has a separate 16- bit-wide data memory space. The data space is accessed using separate Address Generation Units (AGUs) for read and write operations. The data memory maps is shown in Figure 4-3. All Effective Addresses (EAs) in the data memory space are 16 bits wide and point to bytes within the data space ...
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... PIC24HJ12GP201/202 FIGURE 4-3: DATA MEMORY MAP FOR PIC24HJ12GP201/202 DEVICES WITH 1 KB RAM MSB Address 0x0001 2 Kbyte SFR Space 0x07FF 0x0801 1 Kbyte SRAM Space 0x0BFF 0x0C01 0x1FFF 0x2001 0x8001 Optionally Mapped into Program Memory 0xFFFF DS70282D-page 24 LSB 16 bits Address MSb LSb 0x0000 ...
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TABLE 4-1: CPU CORE REGISTERS MAP SFR SFR Name Bit 15 Bit 14 Bit 13 Addr WREG0 0000 WREG1 0002 WREG2 0004 WREG3 0006 WREG4 0008 WREG5 000A WREG6 000C WREG7 000E WREG8 0010 WREG9 0012 WREG10 0014 WREG11 0016 ...
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... CN15PUE CN14PUE CN13PUE CN12PUE CN11PUE CNPU2 006A CN30PUE CN29PUE — — Legend unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. TABLE 4-3: CHANGE NOTIFICATION REGISTER MAP FOR PIC24HJ12GP201 SFR SFR Bit 15 Bit 14 Bit 13 Bit 12 Name Addr ...
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TABLE 4-4: INTERRUPT CONTROLLER REGISTER MAP SFR SFR Bit 15 Bit 14 Bit 13 Bit 12 Name Addr — — — INTCON1 0080 NSTDIS INTCON2 0082 ALTIVT DISI — — IFS0 0084 — — AD1IF U1TXIF IFS1 0086 — — ...
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TABLE 4-5: TIMER REGISTER MAP SFR Name SFR Bit 15 Bit 14 Bit 13 Bit 12 Addr TMR1 0100 PR1 0102 T1CON 0104 TON — TSIDL — TMR2 0106 TMR3HLD 0108 TMR3 010A PR2 010C PR3 010E T2CON 0110 TON ...
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TABLE 4-8: I2C1 REGISTER MAP SFR SFR Name Bit 15 Bit 14 Bit 13 Bit 12 Addr I2C1RCV 0200 — — — — I2C1TRN 0202 — — — — I2C1BRG 0204 — — — — I2C1CON 0206 I2CEN — I2CSIDL ...
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... RPOR7 06CE — — — Legend unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. TABLE 4-13: PERIPHERAL PIN SELECT OUTPUT REGISTER MAP FOR PIC24HJ12GP201 File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 RPOR0 06C0 — ...
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... TABLE 4-14: ADC1 REGISTER MAP FOR PIC24HJ12GP201 File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 ADC1BUF0 0300 ADC1BUF1 0302 ADC1BUF2 0304 ADC1BUF3 0306 ADC1BUF4 0308 ADC1BUF5 030A ADC1BUF6 030C ADC1BUF7 030E ADC1BUF8 0310 ADC1BUF9 0312 ADC1BUFA 0314 ADC1BUFB 0316 ADC1BUFC 0318 ADC1BUFD ...
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TABLE 4-15: ADC1 REGISTER MAP FOR PIC24HJ12GP202 File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 ADC1BUF0 0300 ADC1BUF1 0302 ADC1BUF2 0304 ADC1BUF3 0306 ADC1BUF4 0308 ADC1BUF5 030A ADC1BUF6 030C ADC1BUF7 030E ADC1BUF8 0310 ADC1BUF9 0312 ADC1BUFA 0314 ...
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... LATB13 LATB12 ODCB 02CE ODCB15 ODCB14 ODCB13 ODCB12 Legend unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. TABLE 4-18: PORTB REGISTER MAP FOR PIC24HJ12GP201 File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 TRISB 02C8 TRISB15 TRISB14 — ...
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TABLE 4-19: SYSTEM CONTROL REGISTER MAP File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 RCON 0740 TRAPR IOPUWR — — OSCCON 0742 — COSC<2:0> CLKDIV 0744 ROI DOZE<2:0> PLLFBD 0746 — — — — OSCTUN 0748 — ...
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... SOFTWARE STACK In addition to its use as a working register, the W15 register in the PIC24HJ12GP201/202 devices is also used as a software Stack Pointer. The Stack Pointer always points to the first available free word and grows from lower to higher addresses. It pre-decrements for stack pops and post-increments for stack pushes, as shown in Figure 4-4 ...
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... PIC24HJ12GP201/202 TABLE 4-22: FUNDAMENTAL ADDRESSING MODES SUPPORTED Addressing Mode File Register Direct Register Direct Register Indirect Register Indirect Post-Modified Register Indirect Pre-Modified Register Indirect with Register Offset (Register Indexed) Register Indirect with Literal Offset MOV 4.3.3 MOVE ( ) INSTRUCTIONS Move instructions provide a greater degree of addressing flexibility than other instructions ...
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... Interfacing Program and Data Memory Spaces The PIC24HJ12GP201/202 architecture uses a 24-bit- wide program space and a 16-bit-wide data space. The architecture is also a modified Harvard scheme, mean- ing that data can also be present in the program space. To use this data successfully, it must be accessed in a way that preserves the alignment of information in both spaces ...
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... PIC24HJ12GP201/202 FIGURE 4-5: DATA ACCESS FROM PROGRAM SPACE ADDRESS GENERATION (1) Program Counter (2) Table Operations (1) Program Space Visibility (Remapping) User/Configuration Space Select Note 1: The LSb of program space addresses is always fixed as ‘0’ to maintain word alignment of data in the program and data spaces. 2: Table operations are not required to be word-aligned. Table read operations are permitted in the configuration memory space ...
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... TBLPAG © 2009 Microchip Technology Inc. PIC24HJ12GP201/202 In Byte mode, either the upper or lower byte of the lower program word is mapped to the lower byte of a data address. The upper byte is selected when Byte Select is ‘1’; the lower byte is selected when it is ‘0’. ...
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... PIC24HJ12GP201/202 4.4.3 READING DATA FROM PROGRAM MEMORY USING PROGRAM SPACE VISIBILITY The upper 32 Kbytes of data space may optionally be mapped into any 16K word page of the program space. This option provides transparent access to stored con- stant data from the data space without the need to use special instructions (such as TBLRDL or TBLRDH) ...
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... Flash memory can be programmed in two ways: • In-Circuit Serial Programming™ (ICSP™) programming capability • Run-Time Self-Programming (RTSP) ICSP allows a PIC24HJ12GP201/202 device to be serially programmed while in the end application circuit. This is done with two lines for programming clock and programming data (one of the alternate programming ...
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... PIC24HJ12GP201/202 5.2 RTSP Operation The PIC24HJ12GP201/202 Flash program memory array is organized into rows of 64 instructions or 192 bytes. RTSP allows the user application to erase a page of memory, which consists of eight rows (512 instructions), and to program one row or one word. The 8-row erase pages and single row write rows are edge- aligned from the beginning of program memory, on boundaries of 1536 bytes and 192 bytes, respectively ...
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... Memory word program operation 0010 = No operation 0001 = Memory row program operation 0000 = Program a single Configuration register byte Note 1: These bits can only be Reset on POR. 2: All other combinations of NVMOP<3:0> are unimplemented. © 2009 Microchip Technology Inc. PIC24HJ12GP201/202 (1) U-0 U-0 — — (1) ...
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... PIC24HJ12GP201/202 REGISTER 5-2: NVMKEY: NONVOLATILE MEMORY KEY REGISTER U-0 U-0 U-0 — — — bit 15 W-0 W-0 W-0 bit 7 Legend Satiable only bit R = Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-8 Unimplemented: Read as ‘0’ bit 7-0 NVMKEY< ...
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... W1 MOV W1, NVMKEY BSET NVMCON, #WR NOP NOP © 2009 Microchip Technology Inc. PIC24HJ12GP201/202 4. Write the first 64 instructions from data RAM into the program memory buffers (see Example 5-2). 5. Write the program block to Flash memory: a) Set the NVMOP bits to ‘0001’ to configure for row programming ...
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... PIC24HJ12GP201/202 EXAMPLE 5-2: LOADING THE WRITE BUFFERS ; Set up NVMCON for row programming operations MOV #0x4001, W0 MOV W0, NVMCON ; Set up a pointer to the first program memory location to be written ; program memory selected, and writes enabled MOV #0x0000, W0 MOV W0, TBLPAG MOV #0x6000 Perform the TBLWT instructions to write the latches ...
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... RESETS Note: This data sheet summarizes the features of the PIC24HJ12GP201/202 families of devices not intended compre- hensive reference source. To complement the information in this data sheet, refer to the PIC24H Family Reference Manual, “Section 8. Reset” (DS70229), which is available from the Microchip web site (www ...
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... PIC24HJ12GP201/202 REGISTER 6-1: RCON: RESET CONTROL REGISTER R/W-0 R/W-0 U-0 TRAPR IOPUWR — bit 15 R/W-0 R/W-0 R/W-0 EXTR SWR SWDTEN bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15 TRAPR: Trap Reset Flag bit Trap Conflict Reset has occurred ...
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... Note 1: All of the Reset status bits can be set or cleared in software. Setting one of these bits in software does not cause a device Reset the FWDTEN Configuration bit is ‘1’ (unprogrammed), the WDT is always enabled, regardless of the SWDTEN bit setting. © 2009 Microchip Technology Inc. PIC24HJ12GP201/202 (1) (CONTINUED) Preliminary DS70282D-page 49 ...
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... PIC24HJ12GP201/202 6.1 System Reset The PIC24HJ12GP201/202 family of devices have two types of Reset: • Cold Reset • Warm Reset A cold Reset is the result of a Power-on Reset (POR BOR cold Reset, the FNOSC configuration bits in the FOSC device configuration register selects the device clock source. ...
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... BOR extension time 100 μs maximum T BOR T Programmable 0-128 ms nominal PWRT power-up time delay 900 μs maximum T Fail-safe Clock FSCM Monitor Delay © 2009 Microchip Technology Inc. PIC24HJ12GP201/202 Vbor V BOR T BOR 3 T PWRT T OSCD Reset Time has elapsed. POR ensures the voltage regulator output becomes stable. ...
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... PIC24HJ12GP201/202 6.2 POR A POR circuit ensures the device is reset from power- on. The POR circuit is active until V V threshold and the delay T has elapsed. The POR POR delay T ensures the internal device bias circuits POR become stable. The device supply voltage characteristics must meet ...
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... Refer to “Watchdog Timer (WDT)” for more information on Watchdog Reset. © 2009 Microchip Technology Inc. PIC24HJ12GP201/202 6.7 Trap Conflict Reset If a lower-priority hard trap occurs while a higher-prior- ity trap is being processed, a hard trap conflict Reset occurs. The hard traps include exceptions of priority level 13 through level 15, inclusive ...
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... PIC24HJ12GP201/202 6.9.0.2 UNINITIALIZED W REGISTER RESET Any attempts to use the uninitialized W register as an address pointer will Reset the device. The W register array (with the exception of W15) is cleared during all Resets and is considered uninitialized until written to. 6.9.0.3 SECURITY RESET If a Program Flow Change (PFC) or Vector Flow ...
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... Reset Sequence A device Reset is not a true exception because the interrupt controller is not involved in the Reset process. The PIC24HJ12GP201/202 device clears its registers in response to a Reset, which forces the PC to zero. The digital signal controller then begins program execution at location 0x000000. The user application ...
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... PIC24HJ12GP201/202 FIGURE 7-1: PIC24HJ12GP201/202 INTERRUPT VECTOR TABLE Reset – GOTO Instruction Reset – GOTO Address Reserved Oscillator Fail Trap Vector Address Error Trap Vector Stack Error Trap Vector Math Error Trap Vector Reserved Reserved Reserved Interrupt Vector 0 Interrupt Vector 1 Interrupt Vector 52 ...
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... Microchip Technology Inc. PIC24HJ12GP201/202 AIVT Address Interrupt Source 0x000114 INT0 – External Interrupt 0 0x000116 IC1 – Input Compare 1 0x000118 OC1 – Output Compare 1 0x00011A T1 – Timer1 0x00011C Reserved 0x00011E IC2 – Input Capture 2 0x000120 OC2 – ...
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... PIC24HJ12GP201/202 TABLE 7-1: INTERRUPT VECTORS (CONTINUED) Interrupt Vector Request (IRQ) IVT Address Number Number 54 46 0x000070 55 47 0x000072 56 48 0x000074 57 49 0x000076 58 50 0x000078 59 51 0x00007A 60 52 0x00007C 61 53 0x00007E 62 54 0x000080 63 55 0x000082 64 56 0x000084 65 57 0x000086 66 58 0x000088 67 59 ...
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... Interrupt Control and Status Registers PIC24HJ12GP201/202 devices implement a total of 17 registers for the interrupt controller: • Interrupt Control Register 1 (INTCON1) • Interrupt Control Register 2 (INTCON2) • Interrupt Flag Status Registers (IFSx) • Interrupt Enable Control Registers (IECx) • Interrupt Priority Control Registers (IPCx) • ...
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... PIC24HJ12GP201/202 REGISTER 7-1: SR: CPU STATUS REGISTER U-0 U-0 U-0 — — — bit 15 (3) (3) R/W-0 R/W-0 R/W-0 (2) (2) IPL2 IPL1 IPL0 bit 7 Legend Clear only bit R = Readable bit S = Set only bit W = Writable bit ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-5 IPL< ...
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... CPU interrupt priority level less Note 1: For complete register details, see Register 3-2: “CORCON: Core Control Register”. 2: The IPL3 bit is concatenated with the IPL<2:0> bits (SR<7:5>) to form the CPU Interrupt Priority Level. © 2009 Microchip Technology Inc. PIC24HJ12GP201/202 (1) U-0 U-0 U-0 — ...
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... PIC24HJ12GP201/202 REGISTER 7-3: INTCON1: INTERRUPT CONTROL REGISTER 1 R/W-0 U-0 U-0 NSTDIS — — bit 15 U-0 R/W-0 U-0 — DIV0ERR — bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15 NSTDIS: Interrupt Nesting Disable bit 1 = Interrupt nesting is disabled ...
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... INT1EP: External Interrupt 1 Edge Detect Polarity Select bit 1 = Interrupt on negative edge 0 = Interrupt on positive edge bit 0 INT0EP: External Interrupt 0 Edge Detect Polarity Select bit 1 = Interrupt on negative edge 0 = Interrupt on positive edge © 2009 Microchip Technology Inc. PIC24HJ12GP201/202 U-0 U-0 U-0 — — — U-0 ...
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... PIC24HJ12GP201/202 REGISTER 7-5: IFS0: INTERRUPT FLAG STATUS REGISTER 0 U-0 U-0 R/W-0 — — AD1IF bit 15 R/W-0 R/W-0 R/W-0 T2IF OC2IF IC2IF bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-14 Unimplemented: Read as ‘0’ bit 13 AD1IF: ADC1 Conversion Complete Interrupt Flag Status bit ...
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... IC1IF: Input Capture Channel 1 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 0 INT0IF: External Interrupt 0 Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred © 2009 Microchip Technology Inc. PIC24HJ12GP201/202 Preliminary DS70282D-page 65 ...
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... PIC24HJ12GP201/202 REGISTER 7-6: IFS1: INTERRUPT FLAG STATUS REGISTER 1 U-0 U-0 R/W-0 — — INT2IF bit 15 R/W-0 R/W-0 U-0 IC8IF IC7IF — bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-14 Unimplemented: Read as ‘0’ bit 13 INT2IF: External Interrupt 2 Flag Status bit ...
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... Unimplemented: Read as ‘0’ bit 1 U1EIF: UART1 Error Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 0 Unimplemented: Read as ‘0’ © 2009 Microchip Technology Inc. PIC24HJ12GP201/202 U-0 U-0 U-0 — — — U-0 U-0 U-0 — ...
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... PIC24HJ12GP201/202 REGISTER 7-8: IEC0: INTERRUPT ENABLE CONTROL REGISTER 0 U-0 U-0 R/W-0 — — AD1IE bit 15 R/W-0 R/W-0 R/W-0 T2IE OC2IE IC2IE bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-14 Unimplemented: Read as ‘0’ bit 13 AD1IE: ADC1 Conversion Complete Interrupt Enable bit ...
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... IEC0: INTERRUPT ENABLE CONTROL REGISTER 0 (CONTINUED) bit 1 IC1IE: Input Capture Channel 1 Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 0 INT0IE: External Interrupt 0 Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled © 2009 Microchip Technology Inc. PIC24HJ12GP201/202 Preliminary DS70282D-page 69 ...
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... PIC24HJ12GP201/202 REGISTER 7-9: IEC1: INTERRUPT ENABLE CONTROL REGISTER 0 U-0 U-0 R/W-0 — — INT2IE bit 15 R/W-0 R/W-0 U-0 IC8IE IC7IE — bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-14 Unimplemented: Read as ‘0’ bit 13 INT2IE: External Interrupt 2 Enable bit ...
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... Bit is set bit 15-2 Unimplemented: Read as ‘0’ bit 1 U1EIE: UART1 Error Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 0 Unimplemented: Read as ‘0’ © 2009 Microchip Technology Inc. PIC24HJ12GP201/202 U-0 U-0 U-0 — — — U-0 U-0 U-0 — ...
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... PIC24HJ12GP201/202 REGISTER 7-11: IPC0: INTERRUPT PRIORITY CONTROL REGISTER 0 U-0 R/W-1 R/W-0 — T1IP<2:0> bit 15 U-0 R/W-1 R/W-0 — IC1IP<2:0> bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15 Unimplemented: Read as ‘0’ bit 14-12 T1IP<2:0>: Timer1 Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • ...
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... IC2IP<2:0>: Input Capture Channel 2 Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 3-0 Unimplemented: Read as ‘0’ © 2009 Microchip Technology Inc. PIC24HJ12GP201/202 R/W-0 U-0 R/W-1 — R/W-0 U-0 U-0 — — ...
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... PIC24HJ12GP201/202 REGISTER 7-13: IPC2: INTERRUPT PRIORITY CONTROL REGISTER 2 U-0 R/W-1 R/W-0 — U1RXIP<2:0> bit 15 U-0 R/W-1 R/W-0 — SPI1EIP<2:0> bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15 Unimplemented: Read as ‘0’ bit 14-12 U1RXIP<2:0>: UART1 Receiver Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • ...
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... Unimplemented: Read as ‘0’ bit 2-0 U1TXIP<2:0>: UART1 Transmitter Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled © 2009 Microchip Technology Inc. PIC24HJ12GP201/202 U-0 U-0 U-0 — — — R/W-0 U-0 R/W-1 — ...
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... PIC24HJ12GP201/202 REGISTER 7-15: IPC4: INTERRUPT PRIORITY CONTROL REGISTER 4 U-0 R/W-1 R/W-0 — CNIP<2:0> bit 15 U-0 R/W-1 R/W-0 — MI2C1IP<2:0> bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15 Unimplemented: Read as ‘0’ bit 14-12 CNIP<2:0>: Change Notification Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • ...
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... Unimplemented: Read as ‘0’ bit 2-0 INT1IP<2:0>: External Interrupt 1 Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled © 2009 Microchip Technology Inc. PIC24HJ12GP201/202 R/W-0 U-0 R/W-1 — U-0 U-0 R/W-1 — — ...
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... PIC24HJ12GP201/202 REGISTER 7-17: IPC7: INTERRUPT PRIORITY CONTROL REGISTER 7 U-0 U-0 U-0 — — — bit 15 U-0 R/W-1 R/W-0 — INT2IP<2:0> bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-7 Unimplemented: Read as ‘0’ bit 6-4 INT2IP<2:0>: External Interrupt 2 Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • ...
Page 81
... U1EIP<2:0>: UART1 Error Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 3-0 Unimplemented: Read as ‘0’ © 2009 Microchip Technology Inc. PIC24HJ12GP201/202 U-0 U-0 U-0 — — — R/W-0 U-0 U-0 — ...
Page 82
... PIC24HJ12GP201/202 REGISTER 7-19: INTTREG: INTERRUPT CONTROL AND STATUS REGISTER U-0 U-0 U-0 — — — bit 15 U-0 R-0 R-0 — bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-12 Unimplemented: Read as ‘0’ bit 11-8 ILR: New CPU Interrupt Priority Level bits 1111 = CPU Interrupt Priority Level is 15 • ...
Page 83
... RETFIE instruction to unstack the saved PC value, SRL value and old CPU priority level. © 2009 Microchip Technology Inc. PIC24HJ12GP201/202 7.4.3 TRAP SERVICE ROUTINE A Trap Service Routine (TSR) is coded like an ISR, except that the appropriate trap status flag in the INTCON1 register must be cleared to avoid re-entry into the TSR ...
Page 84
... PIC24HJ12GP201/202 NOTES: DS70282D-page 82 Preliminary © 2009 Microchip Technology Inc. ...
Page 85
... OSCILLATOR CONFIGURATION Note: This data sheet summarizes the features of the PIC24HJ12GP201/202 family of devices. However not intended comprehensive reference source. To complement the information in this data sheet, refer to the “PIC24H Family Reference Manual”, “Oscillator” (DS70227), available from the Microchip web site (www ...
Page 86
... The output of the oscillator (or the output of the PLL if a PLL mode has been selected) F generate the device instruction clock (F peripheral clock time base (F operating speed of the device, and speeds MHz are supported by the PIC24HJ12GP201/202 architecture. Instruction execution speed or device operating fre- quency given by Equation 8-1. ...
Page 87
... MHz ranged needed. • If PLLPOST<1:0> then This provides a Fosc of 160 MHz. The resultant device operating speed is 80 MIPS. FIGURE 8-2: PIC24HJ12GP201/202 PLL BLOCK DIAGRAM Source (Crystal, External Clock or Internal RC) Note 1: This frequency range must be satisfied at all times. TABLE 8-1: ...
Page 88
... PIC24HJ12GP201/202 REGISTER 8-1: OSCCON: OSCILLATOR CONTROL REGISTER U-0 R-0 R-0 — COSC<2:0> bit 15 R/W-0 R/W-0 R-0 CLKLOCK IOLOCK LOCK bit 7 Legend Value set from Configuration bits on POR R = Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15 Unimplemented: Read as ‘0’ ...
Page 89
... Direct clock switches between any primary oscillator mode with PLL and FRCPLL mode are not permitted. This applies to clock switches in either direction. In these instances, the application must switch to FRC mode as a transition clock source between the two PLL modes. © 2009 Microchip Technology Inc. PIC24HJ12GP201/202 (1) (CONTINUED) Preliminary ...
Page 90
... PIC24HJ12GP201/202 REGISTER 8-2: CLKDIV: CLOCK DIVISOR REGISTER R/W-0 R/W-0 R/W-1 ROI DOZE<2:0> bit 15 R/W-0 R/W-1 U-0 PLLPOST<1:0> — bit 7 Legend Value set from Configuration bits on POR R = Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15 ROI: Recover on Interrupt bit ...
Page 91
... PLLDIV<8:0>: PLL Feedback Divisor bits (also denoted as ‘M’, PLL multiplier) 000000000 = 2 000000001 = 3 000000010 = 4 • • • 000110000 = 50 (default) • • • 111111111 = 513 © 2009 Microchip Technology Inc. PIC24HJ12GP201/202 U-0 U-0 U-0 — — — R/W-1 R/W-0 R/W-0 PLLDIV<7:0> Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared ...
Page 92
... PIC24HJ12GP201/202 REGISTER 8-4: OSCTUN: FRC OSCILLATOR TUNING REGISTER U-0 U-0 U-0 — — — bit 15 U-0 U-0 R/W-0 — — bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-6 Unimplemented: Read as ‘0’ bit 5-0 TUN<5:0>: FRC Oscillator Tuning bits 011111 = Center frequency + 11 ...
Page 93
... Applications are free to switch among any of the four clock sources (Primary, LP, FRC and LPRC) under software control at any time. To limit the possible side effects of this flexibility, PIC24HJ12GP201/202 devices have a safeguard lock built into the switch process. Note: Primary Oscillator mode has three different submodes (XT, HS and EC), which are determined by the POSCMD< ...
Page 94
... PIC24HJ12GP201/202 8.3 Fail-Safe Clock Monitor (FSCM) The Fail-Safe Clock Monitor (FSCM) allows the device to continue to operate even in the event of an oscillator failure. The FSCM function is enabled by programming. If the FSCM function is enabled, the LPRC internal oscillator runs at all times (except during Sleep mode) and is not subject to control by the Watchdog Timer ...
Page 95
... Clock Frequency and Clock Switching PIC24HJ12GP201/202 devices allow a wide range of clock frequencies to be selected under application control. If the system clock configuration is not locked, users can choose low-power or high-precision oscillators by simply changing the NOSC bits (OSCCON< ...
Page 96
... PIC24HJ12GP201/202 9.2.2 IDLE MODE The following occur in Idle mode: • The CPU stops executing instructions • The WDT is automatically cleared • The system clock source remains active. By default, all peripheral modules continue to operate normally from the system clock source, but can also be selectively disabled (see Section 9.4 “ ...
Page 97
... ADC1 module is enabled Note 1: PCFGx bits have no effect if the ADC module is disabled by setting this bit. When the bit is set, all port pins that have been multiplexed with ANx will be in Digital mode. © 2009 Microchip Technology Inc. PIC24HJ12GP201/202 R/W-0 R/W-0 U-0 T2MD T1MD — ...
Page 98
... PIC24HJ12GP201/202 REGISTER 9-2: PMD2: PERIPHERAL MODULE DISABLE CONTROL REGISTER 2 R/W-0 R/W-0 U-0 IC8MD IC7MD — bit 15 U-0 U-0 U-0 — — — bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15 IC8MD: Input Capture 8 Module Disable bit ...
Page 99
... I/O PORTS Note: This data sheet summarizes the features of the PIC24HJ12GP201/202 family of devices. However not intended comprehensive reference source. To complement the information in this data sheet, refer to the “PIC24H Family Refer- ence Manual”, Section 30. “I/O Ports with Peripheral Pin Select” (DS70234), which is available from the Microchip web site (www ...
Page 100
... NOP. An example is shown in Example 10-1. 10.3 Input Change Notification The input change notification function of the I/O ports allows the PIC24HJ12GP201/202 devices to generate interrupt requests to the processor in response to a change-of-state on selected input pins. This feature can detect input change-of-states even in Sleep mode, when the clocks are disabled ...
Page 101
... The association of a peripheral to a peripheral selectable pin is handled in two different ways, depending on whether an input or output is being mapped. © 2009 Microchip Technology Inc. PIC24HJ12GP201/202 10.4.2.1 Input Mapping The inputs of the peripheral pin select options are mapped on the basis of the peripheral. A control register associated with a peripheral dictates the pin it will be mapped to ...
Page 102
... PIC24HJ12GP201/202 TABLE 10-1: SELECTABLE INPUT SOURCES (MAPS INPUT TO FUNCTION) Input Name External Interrupt 1 External Interrupt 2 Timer2 External Clock Timer3 External Clock Input Capture 1 Input Capture 2 Input Capture 7 Input Capture 8 Output Compare Fault A UART1 Receive UART1 Clear To Send SPI1 Data Input SPI1 Clock Input ...
Page 103
... IOL1WAY allows user applications unlimited access (with the proper use of the unlock sequence) to the peripheral pin select registers. 10.5 Peripheral Pin Select Registers The PIC24HJ12GP201/202 devices implement 17 registers for remappable peripheral configuration: • Input Remappable Peripheral Registers (9) • Output Remappable Peripheral Registers (8) Note: Input and Output Register values can only be changed if OSCCON< ...
Page 104
... PIC24HJ12GP201/202 REGISTER 10-1: RPINR0: PERIPHERAL PIN SELECT INPUT REGISTER 0 U-0 U-0 U-0 — — — bit 15 U-0 U-0 U-0 — — — bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-13 Unimplemented: Read as ‘0’ bit 12-8 INT1R< ...
Page 105
... INT2R<4:0>: Assign External Interrupt 2 (INTR2) to the corresponding RPn pin bits 11111 = Input tied to V 01111 = Input tied to RP15 • • • 00001 = Input tied to RP1 00000 = Input tied to RP0 © 2009 Microchip Technology Inc. PIC24HJ12GP201/202 U-0 U-0 — — R/W-1 R/W-1 R/W-1 INT2R<4:0> ...
Page 106
... PIC24HJ12GP201/202 REGISTER 10-3: RPINR3: PERIPHERAL PIN SELECT INPUT REGISTER 3 U-0 U-0 U-0 — — — bit 15 U-0 U-0 U-0 — — — bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-13 Unimplemented: Read as ‘0’ bit 12-8 T3CKR< ...
Page 107
... IC1R<4:0>: Assign Input Capture 1 (IC1) to the corresponding RPn pin bits 11111 = Input tied to V 01111 = Input tied to RP15 • • • 00001 = Input tied to RP1 00000 = Input tied to RP0 © 2009 Microchip Technology Inc. PIC24HJ12GP201/202 R/W-1 R/W-1 R/W-1 IC2R<4:0> R/W-1 R/W-1 R/W-1 IC1R<4:0> ...
Page 108
... PIC24HJ12GP201/202 REGISTER 10-5: RPINR10: PERIPHERAL PIN SELECT INPUT REGISTERS 10 U-0 U-0 U-0 — — — bit 15 U-0 U-0 U-0 — — — bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-13 Unimplemented: Read as ‘0’ bit 12-8 IC8R< ...
Page 109
... OCFAR<4:0>: Assign Output Capture A (OCFA) to the corresponding RPn pin bits 11111 = Input tied to V 01111 = Input tied to RP15 • • • 00001 = Input tied to RP1 00000 = Input tied to RP0 © 2009 Microchip Technology Inc. PIC24HJ12GP201/202 U-0 U-0 — — R/W-1 R/W-1 R/W-1 OCFAR<4:0> ...
Page 110
... PIC24HJ12GP201/202 REGISTER 10-7: RPINR18: PERIPHERAL PIN SELECT INPUT REGISTER 18 U-0 U-0 U-0 — — — bit 15 U-0 U-0 U-0 — — — bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-13 Unimplemented: Read as ‘0’ bit 12-8 U1CTSR< ...
Page 111
... SDI1R<4:0>: Assign SPI1 Data Input (SDI1) to the corresponding RPn pin bits 11111 = Input tied to V 01111 = Input tied to RP15 • • • 00001 = Input tied to RP1 00000 = Input tied to RP0 © 2009 Microchip Technology Inc. PIC24HJ12GP201/202 R/W-1 R/W-1 R/W-1 SCK1R<4:0> R/W-1 R/W-1 R/W-1 SDI1R<4:0> ...
Page 112
... PIC24HJ12GP201/202 REGISTER 10-9: RPINR21: PERIPHERAL PIN SELECT INPUT REGISTER 21 U-0 U-0 U-0 — — — bit 15 U-0 U-0 U-0 — — — bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-5 Unimplemented: Read as ‘0’ bit 4-0 SS1R< ...
Page 113
... RP3R<4:0>: Peripheral Output Function is Assigned to RP3 Output Pin bits (see Table 10-2 for peripheral function numbers) bit 7-5 Unimplemented: Read as ‘0’ bit 4-0 RP2R<4:0>: Peripheral Output Function is Assigned to RP2 Output Pin bits (see Table 10-2 for peripheral function numbers) © 2009 Microchip Technology Inc. PIC24HJ12GP201/202 R/W-0 R/W-0 R/W-0 RP1R<4:0> R/W-0 R/W-0 R/W-0 RP0R< ...
Page 114
... PIC24HJ12GP201/202 REGISTER 10-12: RPOR2: PERIPHERAL PIN SELECT OUTPUT REGISTERS 2 U-0 U-0 U-0 — — — bit 15 U-0 U-0 U-0 — — — bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-13 Unimplemented: Read as ‘0’ bit 12-8 RP5R< ...
Page 115
... RP11R<4:0>: Peripheral Output Function is Assigned to RP11 Output Pin bits (see Table 10-2 for peripheral function numbers) bit 7-5 Unimplemented: Read as ‘0’ bit 4-0 RP10R<4:0>: Peripheral Output Function is Assigned to RP10 Output Pin bits (see Table 10-2 for peripheral function numbers) © 2009 Microchip Technology Inc. PIC24HJ12GP201/202 R/W-0 R/W-0 R/W-0 RP9R<4:0> R/W-0 R/W-0 R/W-0 RP8R< ...
Page 116
... PIC24HJ12GP201/202 REGISTER 10-16: RPOR6: PERIPHERAL PIN SELECT OUTPUT REGISTERS 6 U-0 U-0 U-0 — — — bit 15 U-0 U-0 U-0 — — — bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-13 Unimplemented: Read as ‘0’ bit 12-8 RP13R< ...
Page 117
... TIMER1 Note: This data sheet summarizes the features of the PIC24HJ12GP201/202 family of devices not intended comprehensive reference complement the information in this data sheet, refer to the PIC24H Family Reference Manual, “Section 11. Timers” (DS70244), which is available from the Microchip web site (www.microchip.com). ...
Page 118
... PIC24HJ12GP201/202 REGISTER 11-1: T1CON: TIMER1 CONTROL REGISTER R/W-0 U-0 R/W-0 TON — TSIDL bit 15 U-0 R/W-0 R/W-0 — TGATE TCKPS<1:0> bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15 TON: Timer1 On bit 1 = Starts 16-bit Timer1 0 = Stops 16-bit Timer1 bit 14 Unimplemented: Read as ‘ ...
Page 119
... TIMER2/3 FEATURE Note: This data sheet summarizes the features of the PIC24HJ12GP201/202 family of devices not intended comprehensive reference complement the information in this data sheet, refer to the PIC24H Family Reference Manual, “Section 11. Timers” (DS70244), which is available from the Microchip web site (www.microchip.com). ...
Page 120
... PIC24HJ12GP201/202 FIGURE 12-1: TIMER2/3 (32-BIT) BLOCK DIAGRAM T2CK TGATE 1 Set T3IF 0 (2) ADC Event Trigger Equal MSb Reset Read TMR2 Write TMR2 Data Bus<15:0> Note 1: The 32-bit timer control bit, T32, must be set for 32-bit timer/counter operation. All control bits are respective to the T2CON register ...
Page 121
... FIGURE 12-2: TIMER2 (16-BIT) BLOCK DIAGRAM T2CK TGATE 1 Set T2IF 0 Reset Equal © 2009 Microchip Technology Inc. PIC24HJ12GP201/202 1x Gate Sync TMR2 Sync Comparator PR2 Preliminary TCKPS<1:0> TON 2 Prescaler 1, 8, 64, 256 TCS TGATE DS70282D-page 119 ...
Page 122
... PIC24HJ12GP201/202 REGISTER 12-1: T2CON CONTROL REGISTER R/W-0 U-0 R/W-0 TON — TSIDL bit 15 U-0 R/W-0 R/W-0 — TGATE TCKPS<1:0> bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15 TON: Timer2 On bit When T32 = Starts 32-bit Timer2 Stops 32-bit Timer2/3 ...
Page 123
... Note 1: When 32-bit timer operation is enabled (T32 = 1) in the Timer Control register (T2CON<3>), the TSIDL bit must be cleared to operate the 32-bit timer in Idle mode. 2: When the 32-bit timer operation is enabled (T32 = 1) in the Timer Control (T2CON<3>) register, these bits have no effect. © 2009 Microchip Technology Inc. PIC24HJ12GP201/202 U-0 U-0 (1) — ...
Page 124
... PIC24HJ12GP201/202 NOTES: DS70282D-page 122 Preliminary © 2009 Microchip Technology Inc. ...
Page 125
... Microchip (www.microchip.com). The Input Capture module is useful in applications requiring frequency (period) and pulse measurement. The PIC24HJ12GP201/202 devices support up to eight input capture channels. The Input Capture module captures the 16-bit value of the selected Time Base register when an event occurs at the ICx pin. The events that cause a capture event are listed below in three categories: • ...
Page 126
... PIC24HJ12GP201/202 13.1 Input Capture Registers REGISTER 13-1: ICxCON: INPUT CAPTURE x CONTROL REGISTER U-0 U-0 R/W-0 — — ICSIDL bit 15 R/W-0 R/W-0 R/W-0 ICTMR ICI<1:0> bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-14 Unimplemented: Read as ‘0’ ...
Page 127
... OUTPUT COMPARE Note: This data sheet summarizes the features of the PIC24HJ12GP201/202 family of devices. However not intended comprehensive reference source. To complement the information in this data sheet, refer to the “PIC24H Family Reference Manual”, Section 13. “Output Compare” (DS70247), which is available from ...
Page 128
... PIC24HJ12GP201/202 14.1 Output Compare Modes Configure the Output Compare modes by setting the appropriate Output Compare Mode (OCM<2:0>) bits in the Output Compare Control (OCxCON<2:0>) register. Table 14-1 lists the different bit settings for the Output Compare modes. Figure 14-2 illustrates the output compare operation for various modes ...
Page 129
... Compare event toggles OCx pin 010 = Initialize OCx pin high, compare event forces OCx pin low 001 = Initialize OCx pin low, compare event forces OCx pin high 000 = Output compare channel is disabled © 2009 Microchip Technology Inc. PIC24HJ12GP201/202 U-0 U-0 U-0 — ...
Page 130
... PIC24HJ12GP201/202 NOTES: DS70282D-page 128 Preliminary © 2009 Microchip Technology Inc. ...
Page 131
... SERIAL PERIPHERAL INTERFACE (SPI) Note: This data sheet summarizes the features of the PIC24HJ12GP201/202 family of devices. However not intended comprehensive reference source. To complement the information in this data sheet, refer to the “PIC24H Family Reference Manual”, Section 18. “Serial Peripheral Interface (DS70243), which is available from the Microchip web site (www ...
Page 132
... PIC24HJ12GP201/202 REGISTER 15-1: SPIxSTAT: SPIx STATUS AND CONTROL REGISTER R/W-0 U-0 R/W-0 SPIEN — SPISIDL bit 15 U-0 R/C-0 U-0 — SPIROV — bit 7 Legend Clearable bit R = Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15 SPIEN: SPIx Enable bit ...
Page 133
... Note 1: The CKE bit is not used in the Framed SPI modes. Program this bit to ‘0’ for the Framed SPI modes (FRMEN = 1). 2: This bit must be cleared when FRMEN = not set both Primary and Secondary prescalers to a value of 1:1. © 2009 Microchip Technology Inc. PIC24HJ12GP201/202 R/W-0 R/W-0 R/W-0 DISSCK ...
Page 134
... PIC24HJ12GP201/202 REGISTER 15-2: SPI CON1: SPIx CONTROL REGISTER 1 (CONTINUED) X bit 4-2 SPRE<2:0>: Secondary Prescale bits (Master mode) 111 = Secondary prescale 1:1 110 = Secondary prescale 2:1 • • • 000 = Secondary prescale 8:1 bit 1-0 PPRE<1:0>: Primary Prescale bits (Master mode Primary prescale 1:1 ...
Page 135
... FRMDLY: Frame Sync Pulse Edge Select bit 1 = Frame sync pulse coincides with first bit clock 0 = Frame sync pulse precedes first bit clock bit 0 Unimplemented: This bit must not be set to ‘1’ by the user application. © 2009 Microchip Technology Inc. PIC24HJ12GP201/202 U-0 U-0 U-0 — — ...
Page 136
... PIC24HJ12GP201/202 NOTES: DS70282D-page 134 Preliminary © 2009 Microchip Technology Inc. ...
Page 137
... INTER-INTEGRATED CIRCUIT™ Note: This data sheet summarizes the features of the PIC24HJ12GP201/202 family of devices. However not intended comprehensive reference source. To complement the information in this data sheet, refer to the “PIC24H Family Reference Manual”, Section 19. “Inter- 2 Integrated Circuit™ (I C™)” (DS70235), which is available from the Microchip web site (www ...
Page 138
... PIC24HJ12GP201/202 2 FIGURE 16-1: I C™ BLOCK DIAGRAM ( Shift SCLx Clock SDAx Shift Clock BRG Down Counter DS70282D-page 136 = 1) X I2CxRCV I2CxRSR LSb Address Match Match Detect I2CxADD Start and Stop Bit Detect Start and Stop Bit Generation Collision Detect Acknowledge Generation ...
Page 139
... General call address disabled bit 6 STREN: SCLx Clock Stretch Enable bit (when operating as I Used in conjunction with SCLREL bit Enable software or receive clock stretching 0 = Disable software or receive clock stretching © 2009 Microchip Technology Inc. PIC24HJ12GP201/202 R/W-1 HC R/W-0 R/W-0 SCLREL IPMIEN A10M ...
Page 140
... PIC24HJ12GP201/202 REGISTER 16-1: I2CxCON: I2Cx CONTROL REGISTER (CONTINUED) bit 5 ACKDT: Acknowledge Data bit (when operating as I Value that will be transmitted when the software initiates an Acknowledge sequence Send NACK during Acknowledge 0 = Send ACK during Acknowledge bit 4 ACKEN: Acknowledge Sequence Enable bit 2 (when operating master, applicable during master receive Initiate Acknowledge sequence on SDAx and SCLx pins and transmit ACKDT data bit ...
Page 141
... Hardware clear at device address match. Hardware set by reception of slave byte. bit 4 P: Stop bit 1 = Indicates that a Stop bit has been detected last 0 = Stop bit was not detected last Hardware set or clear when Start, Repeated Start or Stop detected. © 2009 Microchip Technology Inc. PIC24HJ12GP201/202 U-0 U-0 R/C-0 HS — — R/C-0 HSC ...
Page 142
... PIC24HJ12GP201/202 REGISTER 16-2: I2CxSTAT: I2Cx STATUS REGISTER (CONTINUED) bit 3 S: Start bit 1 = Indicates that a Start (or Repeated Start) bit has been detected last 0 = Start bit was not detected last Hardware set or clear when Start, Repeated Start or Stop detected. bit 2 R_W: Read/Write Information bit (when operating Read – ...
Page 143
... AMSKx: Mask for Address bit x Select bit 1 = Enable masking for bit x of incoming message address; bit match not required in this position 0 = Disable masking for bit x; bit match required in this position © 2009 Microchip Technology Inc. PIC24HJ12GP201/202 U-0 U-0 U-0 — ...
Page 144
... PIC24HJ12GP201/202 NOTES: DS70282D-page 142 Preliminary © 2009 Microchip Technology Inc. ...
Page 145
... Microchip web site (www.microchip.com). The Universal Asynchronous Receiver Transmitter (UART) module is one of the serial I/O modules available in the PIC24HJ12GP201/202 device family. The UART is a full-duplex asynchronous system that can communicate with peripheral devices, such as personal computers, LIN, and RS-232, and RS-485 interfaces ...
Page 146
... PIC24HJ12GP201/202 REGISTER 17-1: UxMODE: UART R/W-0 U-0 R/W-0 (1) UARTEN — USIDL bit 15 R/W-0 HC R/W-0 R/W-0 HC WAKE LPBACK ABAUD bit 7 Legend Hardware cleared R = Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15 UARTEN: UARTx Enable bit 1 = UARTx is enabled; all UARTx pins are controlled by UARTx as defined by UEN<1:0> ...
Page 147
... Note 1: Refer to Section 17. “UART” (DS70232) in the “PIC24H Family Reference Manual” for information on enabling the UART module for receive or transmit operation. 2: This feature is only available for the 16x BRG mode (BRGH = 0). © 2009 Microchip Technology Inc. PIC24HJ12GP201/202 MODE REGISTER (CONTINUED) x Preliminary ...
Page 148
... PIC24HJ12GP201/202 REGISTER 17-2: U STA: UART x R/W-0 R/W-0 R/W-0 UTXISEL1 UTXINV UTXISEL0 bit 15 R/W-0 R/W-0 R/W-0 URXISEL<1:0> ADDEN bit 7 Legend Hardware cleared R = Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15,13 UTXISEL<1:0>: Transmission Interrupt Mode Selection bits 11 = Reserved; do not use ...
Page 149
... Receive buffer has data, at least one more character can be read 0 = Receive buffer is empty Note 1: Refer to Section 17. “UART” (DS70232) in the “PIC24H Family Reference Manual” for information on enabling the UART module for transmit operation. © 2009 Microchip Technology Inc. PIC24HJ12GP201/202 STATUS AND CONTROL REGISTER (CONTINUED) x Preliminary DS70282D-page 147 ...
Page 150
... PIC24HJ12GP201/202 NOTES: DS70282D-page 148 Preliminary © 2009 Microchip Technology Inc. ...
Page 151
... Manual”, Section 28. “Analog-to- Digital Converter (ADC) without DMA” (DS70249), which is available from the Microchip web site (www.microchip.com). The PIC24HJ12GP201/202 devices have ADC module input channels. The AD12B bit (AD1CON1<10>), allows each of the ADC modules to be configured as either a 10- bit, 4-sample-and-hold ADC (default configuration 12-bit, 1-sample-and-hold ADC ...
Page 152
... PIC24HJ12GP201/202 FIGURE 18-1: ADC BLOCK DIAGRAM FOR PIC24HJ12GP201 DEVICES AN0 AN7 CHANNEL SCAN CH0SB<4:0> CH0SA<4:0> CH0 CSCNA AN1 V - REF CH0NA CH0NB AN0 AN3 CH123SA CH123SB (2) CH1 AN6 V - REF CH123NA CH123NB AN1 CH123SA CH123SB (2) CH2 AN7 V - REF CH123NA CH123NB AN2 CH123SA CH123SB ...
Page 153
... AN5 CH123SA CH123SB (2) CH3 AN8 V - REF CH123NA CH123NB Alternate Input Selection Note inputs can be multiplexed with other analog inputs. REF REF 2: Channels 1, 2, and 3 are not applicable for the 12-bit mode of operation. © 2009 Microchip Technology Inc. PIC24HJ12GP201/202 Preliminary (1) ( ...
Page 154
... PIC24HJ12GP201/202 FIGURE 18-3: ADC CONVERSION CLOCK PERIOD BLOCK DIAGRAM ADC Internal (2) RC Clock T CY OSC ( Note 1: Refer to Figure 8-2 for the derivation of Fosc when the PLL is enabled. If the PLL is not used, F the clock source frequency See the ADC electrical characteristics for the exact RC clock value. ...
Page 155
... SIMSAM: Simultaneous Sample Select bit (applicable only when CHPS<1:0> 1x) When AD12B = 1, SIMSAM is: U-0, Unimplemented, Read as ‘0’ Samples CH0, CH1, CH2, CH3 simultaneously (when CHPS<1:0> = 1x); or Samples CH0 and CH1 simultaneously (when CHPS<1:0> Samples multiple channels individually in sequence © 2009 Microchip Technology Inc. PIC24HJ12GP201/202 U-0 U-0 — — U-0 R/W-0 — ...
Page 156
... PIC24HJ12GP201/202 REGISTER 18-1: AD1CON1: ADC1 CONTROL REGISTER 1 (CONTINUED) bit 2 ASAM: ADC Sample Auto-Start bit 1 = Sampling begins immediately after last conversion. SAMP bit is auto-set Sampling begins when SAMP bit is set bit 1 SAMP: ADC Sample Enable bit 1 = ADC sample-and-hold amplifiers are sampling 0 = ADC sample-and-hold amplifiers are holding If ASAM = 0, software can write ‘ ...
Page 157
... Always starts filling buffer from the beginning bit 0 ALTS: Alternate Input Sample Mode Select bit 1 = Uses channel input selects for Sample A on first sample and Sample B on next sample 0 = Always uses channel input selects for Sample A © 2009 Microchip Technology Inc. PIC24HJ12GP201/202 U-0 U-0 — — R/W-0 R/W-0 SMPI< ...
Page 158
... PIC24HJ12GP201/202 REGISTER 18-3: AD1CON3: ADC1 CONTROL REGISTER 3 R/W-0 U-0 U-0 ADRC — — bit 15 U-0 U-0 R/W-0 bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15 ADRC: ADC Conversion Clock Source bit 1 = ADC internal RC clock 0 = Clock derived from system clock bit 14-13 Unimplemented: Read as ‘ ...
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... R = Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-11 Unimplemented: Read as ‘0’ bit 10-9 CH123NB<1:0>: Channel Negative Input Select for Sample B bits PIC24HJ12GP201 devices only: If AD12B = Reserved 10 = Reserved 01 = Reserved 00 = Reserved If AD12B = Reserved 10 = CH1 negative input is AN6, CH2 negative input is AN7, CH3 negative input is not connected ...
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... CH1 positive input is AN3, CH2 positive input is AN4, CH3 positive input is AN5 0 = CH1 positive input is AN0, CH2 positive input is AN1, CH3 positive input is AN2 bit 7-3 Unimplemented: Read as ‘0’ bit 2-1 CH123NA<1:0>: Channel Negative Input Select for Sample A bits PIC24HJ12GP201 devices only: If AD12B = Reserved 10 = Reserved 01 = Reserved 00 = Reserved ...
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... REGISTER 18-4: AD1CHS123: ADC1 INPUT CHANNEL SELECT REGISTER (CONTINUED) bit 0 CH123SA: Channel Positive Input Select for Sample A bit PIC24HJ12GP201 devices only: If AD12B = Reserved 0 = Reserved If AD12B = CH1 positive input is AN3, CH2 and CH3 positive inputs are not connected 0 = CH1 positive input is AN0, CH2 positive input is AN1, CH3 positive input is AN2 ...
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... Channel 0 negative input is V bit 14-13 Unimplemented: Read as ‘0’ bit 12-8 CH0SB<4:0>: Channel 0 Positive Input Select for Sample B bits PIC24HJ12GP201 devices only: 00111 = Channel 0 positive input is AN7 00110 = Channel 0 positive input is AN6 00101 = Reserved 00100 = Reserved 00011 = Channel 0 positive input is AN3 ...
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... REGISTER 18-5: AD1CHS0: ADC1 INPUT CHANNEL 0 SELECT REGISTER (CONTINUED) bit 4-0 CH0SA<4:0>: Channel 0 Positive Input Select for Sample A bits PIC24HJ12GP201 devices only: 00111 = Channel 0 positive input is AN7 00110 = Channel 0 positive input is AN6 00101 = Reserved 00100 = Reserved 00011 = Channel 0 positive input is AN3 ...
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... PIC24HJ12GP201/202 REGISTER 18-6: AD1CSSL: ADC1 INPUT SCAN SELECT REGISTER LOW U-0 U-0 U-0 — — — bit 15 R/W-0 R/W-0 R/W-0 CSS7 CSS6 CSS5 bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-10 Unimplemented: Read as ‘0’ ...
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... SPECIAL FEATURES Note: This data sheet summarizes the features of the PIC24HJ12GP201/202 devices not intended comprehensive reference source. To complement the information in this data sheet, refer to the “PIC24H Family Reference Please see the Microchip web site (www.microchip.com) for the latest family reference manual sections. ...
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... PIC24HJ12GP201/202 TABLE 19-2: PIC24HJ12GP201/202 CONFIGURATION BITS DESCRIPTION Bit Field Register BWRP FBS BSS<2:0> FBS GSS<1:0> FGS GWRP FGS IESO FOSCSEL FNOSC<2:0> FOSCSEL FCKSM<1:0> FOSC IOL1WAY FOSC OSCIOFNC FOSC POSCMD<1:0> FOSC DS70282D-page 164 Description Boot Segment Program Flash Write Protection 1 = Boot segment may be written ...
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... TABLE 19-2: PIC24HJ12GP201/202 CONFIGURATION BITS DESCRIPTION (CONTINUED) Bit Field Register FWDTEN FWDT WINDIS FWDT WDTPRE FWDT WDTPOST<3:0> FWDT ALTI2C FPOR FPWRT<2:0> FPOR JTAGEN FICD ICS<1:0> FICD © 2009 Microchip Technology Inc. PIC24HJ12GP201/202 Description Watchdog Timer Enable bit 1 = Watchdog Timer always enabled (LPRC oscillator cannot be disabled. ...
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... This can create a conflict for designs that are required to operate at a higher typical voltage, such as 3.3V. To simplify system design, all devices in the PIC24HJ12GP201/202 family incorporate an on-chip regulator that allows the device to run its core logic from V ...
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... Watchdog Timer (WDT) For PIC24HJ12GP201/202 devices, the WDT is driven by the LPRC oscillator. When the WDT is enabled, the clock source is also enabled. 19.4.1 PRESCALER/POSTSCALER The nominal WDT clock source from LPRC is 32 kHz. This feeds a prescaler than can be configured for either 5-bit (divide-by-32) or 7-bit (divide-by-128) operation ...
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... PIC24HJ12GP201/202 19.5 JTAG Interface PIC24HJ12GP201/202 devices implement a JTAG interface, which supports boundary scan device test- ing, as well as in-circuit programming. Detailed infor- mation on this interface will be provided in future revisions of the document. 19.6 Code Protection and CodeGuard™ Security The PIC24HJ12GP201/202 devices intermediate implementation of CodeGuard Security. ...
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... In-Circuit Serial Programming PIC24HJ12GP201/202 family digital signal controllers can be serially programmed while in the end application circuit. This is done with two lines for clock and data and three other lines for power, ground and the programming sequence. Serial programming allows customers ...
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... PIC24HJ12GP201/202 NOTES: DS70282D-page 170 Preliminary © 2009 Microchip Technology Inc. ...
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... INSTRUCTION SET SUMMARY Note: This data sheet summarizes the features of this group of PIC24HJ12GP201/202 devices not intended comprehensive reference complement the information in this data sheet, refer to the latest “PIC24H Family Reference Manual” sections, which are available from the Microchip web site (www ...
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... PIC24HJ12GP201/202 TABLE 20-1: SYMBOLS USED IN OPCODE DESCRIPTIONS Field #text Means literal defined by “text” (text) Means “content of text” [text] Means “the location addressed by text” Optional field or operation <n:m> Register bit field .b Byte mode selection .d Double Word mode selection .S Shadow register select ...
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... BTG f,#bit4 BTG Ws,#bit4 10 BTSC BTSC f,#bit4 BTSC Ws,#bit4 11 BTSS BTSS f,#bit4 BTSS Ws,#bit4 © 2009 Microchip Technology Inc. PIC24HJ12GP201/202 Description WREG WREG = f + WREG Wd = lit10 + lit5 WREG + (C) WREG = f + WREG + ( lit10 + lit5 + ( .AND. WREG WREG = f .AND. WREG Wd = lit10 .AND .AND .AND. lit5 ...
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... PIC24HJ12GP201/202 TABLE 20-2: INSTRUCTION SET OVERVIEW (CONTINUED) Base Assembly Instr Assembly Syntax Mnemonic # 12 BTST BTST f,#bit4 BTST.C Ws,#bit4 BTST.Z Ws,#bit4 BTST.C Ws,Wb BTST.Z Ws,Wb 13 BTSTS BTSTS f,#bit4 BTSTS.C Ws,#bit4 BTSTS.Z Ws,#bit4 14 CALL CALL lit23 CALL Wn 15 CLR CLR f CLR WREG CLR ...
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... Wnd POP.S 45 PUSH PUSH f PUSH Wso PUSH.D Wns PUSH.S 46 PWRSAV PWRSAV #lit1 © 2009 Microchip Technology Inc. PIC24HJ12GP201/202 Description WREG = WREG = .IOR. WREG WREG = f .IOR. WREG Wd = lit10 .IOR .IOR .IOR. lit5 Link Frame Pointer f = Logical Right Shift f WREG = Logical Right Shift f ...
Page 178
... PIC24HJ12GP201/202 TABLE 20-2: INSTRUCTION SET OVERVIEW (CONTINUED) Base Assembly Instr Assembly Syntax Mnemonic # 47 RCALL RCALL Expr RCALL Wn 48 REPEAT REPEAT #lit14 REPEAT Wn 49 RESET RESET 50 RETFIE RETFIE 51 RETLW RETLW #lit10,Wn 52 RETURN RETURN 53 RLC RLC f RLC f,WREG RLC Ws,Wd 54 RLNC RLNC f RLNC ...
Page 179
... XOR f XOR f,WREG XOR #lit10,Wn XOR Wb,Ws,Wd XOR Wb,#lit5, Ws,Wnd © 2009 Microchip Technology Inc. PIC24HJ12GP201/202 Description Read Prog<15:0> Write Ws<7:0> to Prog<23:16> Write Ws to Prog<15:0> Unlink Frame Pointer .XOR. WREG WREG = f .XOR. WREG Wd = lit10 .XOR .XOR .XOR. lit5 Wnd = Zero-extend Ws Preliminary # ...
Page 180
... PIC24HJ12GP201/202 NOTES: DS70282D-page 178 Preliminary © 2009 Microchip Technology Inc. ...
Page 181
... MPLAB PM3 Device Programmer - PICkit™ 2 Development Programmer • Low-Cost Demonstration and Development Boards and Evaluation Kits © 2009 Microchip Technology Inc. PIC24HJ12GP201/202 21.1 MPLAB Integrated Development Environment Software The MPLAB IDE software brings an ease of software development previously unseen in the 8/16-bit micro- controller market ...
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... PIC24HJ12GP201/202 21.2 MPASM Assembler The MPASM Assembler is a full-featured, universal macro assembler for all PIC MCUs. The MPASM Assembler generates relocatable object files for the MPLINK Object Linker, Intel files, MAP files to detail memory usage and symbol reference, absolute LST files that contain source lines and generated machine code and COFF files for debugging ...
Page 183
... Microchip Technology Inc. PIC24HJ12GP201/202 21.9 MPLAB ICD 2 In-Circuit Debugger Microchip’s In-Circuit Debugger, MPLAB ICD powerful, ...
Page 184
... PIC24HJ12GP201/202 21.11 PICSTART Plus Development Programmer The PICSTART Plus Development Programmer is an easy-to-use, low-cost, prototype programmer. It connects to the PC via a COM (RS-232) port. MPLAB Integrated Development Environment software makes using the programmer simple and efficient. The PICSTART Plus Development Programmer supports most PIC devices in DIP packages pins. ...
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... This section provides an overview of PIC24HJ12GP201/202 electrical characteristics. Additional information will be provided in future revisions of this document as it becomes available. Absolute maximum ratings for the PIC24HJ12GP201/202 family are listed below. Exposure to these maximum rating conditions for extended periods can affect device reliability. Functional operation of the device at these or any other conditions above the parameters indicated in the operation listings of this specification is not implied ...
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... Symbol DMAX Symbol θ JA θ JA θ JA θ JA θ JA θ JA θ numbers are achieved by package simulations Preliminary Max MIPS PIC24HJ12GP201/202 40 40 Min Typ Max Unit -40 — +125 °C -40 — +85 °C -40 — +140 °C -40 — +125 ° INT – T )/θ Typ ...
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... DD 3: These parameters are characterized by similarity, but are not tested in manufacturing voltage must remain at Vss for a minimum of 200 µs to ensure POR. DD © 2009 Microchip Technology Inc. PIC24HJ12GP201/202 Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature (1) Min Typ Max 3.0 — ...
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... PIC24HJ12GP201/202 TABLE 22-5: DC CHARACTERISTICS: OPERATING CURRENT (I DC CHARACTERISTICS Parameter (1) Typical Max No. (2) Operating Current ( DC20d 24 30 DC20a 27 30 DC20b 27 30 DC20c 27 35 DC21d 30 40 DC21a 31 40 DC21b 32 45 DC21c 33 45 DC22d 35 50 DC22a 38 50 DC22b 38 55 DC22c 39 55 DC23d 47 70 DC23a ...
Page 189
... Peripheral Module IDLE Disable SFR registers are zeroed. All I/O pins are configured as inputs and pulled These parameters are characterized, but are not tested in manufacturing. © 2009 Microchip Technology Inc. PIC24HJ12GP201/202 ) IDLE Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) -40°C ≤ T ≤ ...
Page 190
... PIC24HJ12GP201/202 TABLE 22-7: DC CHARACTERISTICS: POWER-DOWN CURRENT (I DC CHARACTERISTICS Parameter (1) Typical Max No. (2) Power-Down Current ( DC60d 55 500 DC60a 63 500 DC60b 85 500 DC60c 146 1000 DC61d 8 13 DC61a 10 15 DC61b 12 20 DC61c 13 25 Note 1: Data in the Typical column is at 3.3V, 25°C unless otherwise stated. ...
Page 191
... Higher leakage current may be measured at different input voltages. 3: Negative current is defined as current sourced by the pin. 4: See “Pin Diagrams” for a list of 5V tolerant pins. © 2009 Microchip Technology Inc. PIC24HJ12GP201/202 Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) -40°C ≤ T Operating temperature -40°C ≤ T (1) ...
Page 192
... PIC24HJ12GP201/202 TABLE 22-10: DC CHARACTERISTICS: I/O PIN OUTPUT SPECIFICATIONS DC CHARACTERISTICS Param Symbol Characteristic No. V Output Low Voltage OL DO10 I/O ports DO16 OSC2/CLKO V Output High Voltage OH DO20 I/O ports DO26 OSC2/CLKO TABLE 22-11: ELECTRICAL CHARACTERISTICS: BOR DC CHARACTERISTICS Param Symbol Characteristic No. BO10 V BOR Event on V ...
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... TABLE 22-13: INTERNAL VOLTAGE REGULATOR SPECIFICATIONS DC CHARACTERISTICS Param Symbol Characteristics No. C External Filter Capacitor EFC Value © 2009 Microchip Technology Inc. PIC24HJ12GP201/202 Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) -40°C ≤ T Operating temperature -40°C ≤ T (3) (1) Min Typ Max Units 10,000 — ...
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... PIC24HJ12GP201/202 22.2 AC Characteristics and Timing Parameters The information contained in this section defines PIC24HJ12GP201/202 AC characteristics and timing parameters. TABLE 22-14: TEMPERATURE AND VOLTAGE SPECIFICATIONS – CHARACTERISTICS FIGURE 22-1: LOAD CONDITIONS FOR DEVICE TIMING SPECIFICATIONS Load Condition 1 – for all pins except OSC2 ...
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... Measurements are taken in EC mode. The CLKO signal is measured on the OSC2 pin. 4: These parameters are characterized by similarity, but are tested in manufacturing These parameters are characterized by similarity, but are not tested in manufacturing. 6: Data for this parameter is preliminary. This parameter is characterized, but is not tested in manufacturing. © 2009 Microchip Technology Inc. PIC24HJ12GP201/202 OS20 OS30 ...
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... PIC24HJ12GP201/202 TABLE 22-17: PLL CLOCK TIMING SPECIFICATIONS (V AC CHARACTERISTICS Param Symbol Characteristic No. OS50 F PLL Voltage Controlled PLLI Oscillator (VCO) Input Frequency Range OS51 F On-Chip VCO System SYS (3) Frequency OS52 T PLL Start-up Time (Lock Time) LOCK OS53 D CLKO Stability (Jitter) CLK Note 1: Data in “ ...
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... CNx High or Low Time (input) RBP Note 1: Data in “Typ” column is at 3.3V, 25°C unless otherwise stated. 2: These parameters are characterized, but are not tested in manufacturing. © 2009 Microchip Technology Inc. PIC24HJ12GP201/202 DI35 DI40 New Value DO31 DO32 Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) -40° ...
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... PIC24HJ12GP201/202 FIGURE 22-4: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP TIMER TIMING CHARACTERISTICS V DD SY12 MCLR Internal POR SY11 PWRT Time-out SY30 OSC Time-out Internal Reset Watchdog Timer Reset I/O Pins SY35 FSCM Delay Note: Refer to Figure 22-1 for load conditions. ...
Page 199
... These parameters are characterized but not tested in manufacturing. 2: Data in “Typ” column is at 3.3V, 25°C unless otherwise stated. 3: These parameters are characterized, but are not tested in manufacturing. © 2009 Microchip Technology Inc. PIC24HJ12GP201/202 Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) -40°C ≤ T Operating temperature -40°C ≤ T ...
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... PIC24HJ12GP201/202 FIGURE 22-5: TIMER1, 2 AND 3 EXTERNAL CLOCK TIMING CHARACTERISTICS TxCK TMRx Note: Refer to Figure 22-1 for load conditions. TABLE 22-22: TIMER1 EXTERNAL CLOCK TIMING REQUIREMENTS AC CHARACTERISTICS Param Symbol Characteristic No. TA10 T H TxCK High Time TX TA11 T L TxCK Low Time TX TA15 T P TxCK Input Period Synchronous, ...