PIC24HJ12GP201-I/SO Microchip Technology, PIC24HJ12GP201-I/SO Datasheet - Page 148
![IC PIC MCU FLASH 4KX24 18SOIC](/photos/6/76/67656/150-18-soic_sml.jpg)
PIC24HJ12GP201-I/SO
Manufacturer Part Number
PIC24HJ12GP201-I/SO
Description
IC PIC MCU FLASH 4KX24 18SOIC
Manufacturer
Microchip Technology
Series
PIC® 24Hr
Datasheets
1.PIC24HJ12GP201-ISO.pdf
(242 pages)
2.PIC24HJ12GP201-ISO.pdf
(8 pages)
3.PIC24HJ12GP201-ISO.pdf
(84 pages)
4.PIC24HJ12GP201-ISO.pdf
(12 pages)
5.PIC24HJ12GP201-IP.pdf
(234 pages)
Specifications of PIC24HJ12GP201-I/SO
Program Memory Type
FLASH
Program Memory Size
12KB (4K x 24)
Package / Case
18-SOIC (7.5mm Width)
Core Processor
PIC
Core Size
16-Bit
Speed
40 MIPs
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
13
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 6x10b/12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
PIC24HJ
Core
PIC
Data Bus Width
16 bit
Data Ram Size
1 KB
Interface Type
I2C/SPI/UART
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
13
Number Of Timers
3
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52713-733, 52714-737, 53276-922, EWDSPIC
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120
Minimum Operating Temperature
- 40 C
On-chip Adc
6-ch x 10-bit or 6-ch x 12-bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
AC164339 - MODULE SKT FOR PM3 28SOIC
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC24HJ12GP201-I/SO
Manufacturer:
MICROCHIP
Quantity:
4 000
PIC24HJ12GP201/202
REGISTER 17-2:
DS70282D-page 146
bit 15
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 15,13
bit 14
bit 12
bit 11
bit 10
bit 9
bit 8
bit 7-6
UTXISEL1
Note 1: Refer to Section 17. “UART” (DS70232) in the “PIC24H Family Reference Manual” for information on
R/W-0
R/W-0
URXISEL<1:0>
enabling the UART module for transmit operation.
UTXISEL<1:0>: Transmission Interrupt Mode Selection bits
11 = Reserved; do not use
10 = Interrupt when a character is transferred to the Transmit Shift Register, and as a result, the
01 = Interrupt when the last character is shifted out of the Transmit Shift Register; all transmit
00 = Interrupt when a character is transferred to the Transmit Shift Register (this implies there is
UTXINV: Transmit Polarity Inversion bit
If IREN = 0:
1 = UxTX Idle state is ‘0’
0 = UxTX Idle state is ‘1’
If IREN = 1:
1 = IrDA
0 = IrDA
Unimplemented: Read as ‘0’
UTXBRK: Transmit Break bit
1 = Send Sync Break on next transmission – Start bit, followed by twelve ‘0’ bits, followed by Stop bit;
0 = Sync Break transmission disabled or completed
UTXEN: Transmit Enable bit
1 = Transmit enabled, UxTX pin controlled by UARTx
0 = Transmit disabled, any pending transmission is aborted and buffer is reset. UxTX pin controlled
UTXBF: Transmit Buffer Full Status bit (read-only)
1 = Transmit buffer is full
0 = Transmit buffer is not full, at least one more character can be written
TRMT: Transmit Shift Register Empty bit (read-only)
1 = Transmit Shift Register is empty and transmit buffer is empty (the last transmission has completed)
0 = Transmit Shift Register is not empty, a transmission is in progress or queued
URXISEL<1:0>: Receive Interrupt Mode Selection bits
11 = Interrupt is set on UxRSR transfer making the receive buffer full (i.e., has 4 data characters)
10 = Interrupt is set on UxRSR transfer making the receive buffer 3/4 full (i.e., has 3 data characters)
0x = Interrupt is set when any character is received and transferred from the UxRSR to the receive
UTXINV
R/W-0
R/W-0
cleared by hardware upon completion
by port.
at least one character open in the transmit buffer)
transmit buffer becomes empty
operations are completed
buffer. Receive buffer has one or more characters.
U
x
STA: UART
®
®
encoded UxTX Idle state is ‘1’
encoded UxTX Idle state is ‘0’
HC = Hardware cleared
W = Writable bit
‘1’ = Bit is set
UTXISEL0
ADDEN
R/W-0
R/W-0
x
STATUS AND CONTROL REGISTER
(1)
RIDLE
U-0
R-1
Preliminary
—
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
R/W-0 HC
UTXBRK
PERR
R-0
UTXEN
R/W-0
FERR
R-0
(1)
© 2009 Microchip Technology Inc.
x = Bit is unknown
UTXBF
OERR
R/C-0
R-0
URXDA
TRMT
R-1
R-0
bit 8
bit 0