PIC16F914-I/PT Microchip Technology, PIC16F914-I/PT Datasheet - Page 268

• Manufacturer Part Number: PIC16F914-I/PT
• Description: IC PIC MCU FLASH 4KX14 44TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 16Fr

Specifications of PIC16F914-I/PT

• Program Memory Type: FLASH
• Program Memory Size: 7KB (4K x 14)
• Package / Case: 44-TQFP, 44-VQFP
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LCD, POR, PWM, WDT
• Number Of I /o: 35
• Eeprom Size: 256 x 8
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC16F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 256 B
• Interface Type: SSP/I2C/AUSART/SPI
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 35
• Number Of Timers: 3
• Operating Supply Voltage: 2 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, DV164120, DM163029
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8-ch x 10-bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: XLT44PT3 - SOCKET TRAN ICE 44MQFP/TQFPAC164305 - MODULE SKT FOR PM3 44TQFP444-1001 - DEMO BOARD FOR PICMICRO MCUAC164020 - MODULE SKT PROMATEII 44TQFP
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

PIC16F91X
Timing Diagrams
Timing Parameter Symbology........................................... 230
Timing Requirements
TMR1H Register ................................................................. 85
TMR1L Register .................................................................. 85
DS41250B-page 266
A/D Conversion ......................................................... 246
Asynchronous Master Transmission ......................... 132
Asynchronous Master Transmission (Back to Back). 132
Asynchronous Reception .......................................... 135
Asynchronous Reception with Address Byte First .... 137
Asynchronous Reception with Address Detect ......... 137
Brown-out Reset (BOR) ............................................ 234
Brown-out Reset Situations ...................................... 189
Capture/Compare/PWM............................................ 237
CLKO and I/O ........................................................... 233
Clock Synchronization .............................................. 176
Comparator Output ..................................................... 94
External Clock ........................................................... 231
Fail-Safe Clock Monitor (FSCM) ................................. 42
I
I
I
I
I
I
INT Pin Interrupt........................................................ 197
LCD Interrupt Timing in Quarter-Duty Cycle Drive.... 121
LCD Sleep Entry/Exit when SLPEN = 1 or CS = 00 . 123
Reset, WDT, OST and Power-up Timer ................... 234
Slave Synchronization .............................................. 166
SPI Master Mode (CKE = 1, SMP = 1) ..................... 240
SPI Mode (Master Mode) .......................................... 165
SPI Mode (Slave Mode with CKE = 0) ...................... 167
SPI Mode (Slave Mode with CKE = 1) ...................... 167
SPI Slave Mode (CKE = 0) ....................................... 241
SPI Slave Mode (CKE = 1) ....................................... 241
Synchronous Reception (Master Mode, SREN) ....... 141
Synchronous Transmission....................................... 139
Synchronous Transmission (Through TXEN) ........... 139
Time-out Sequence
Timer0 and Timer1 External Clock ........................... 235
Timer1 Incrementing Edge.......................................... 86
Two Speed Start-up .................................................... 41
Type-A in 1/2 Mux, 1/2 Bias Drive ............................ 111
Type-A in 1/2 Mux, 1/3 Bias Drive ............................ 113
Type-A in 1/3 Mux, 1/2 Bias Drive ............................ 115
Type-A in 1/3 Mux, 1/3 Bias Drive ............................ 117
Type-A in 1/4 Mux, 1/3 Bias Drive ............................ 119
Type-A/Type-B in Static Drive................................... 110
Type-B in 1/2 Mux, 1/2 Bias Drive ............................ 112
Type-B in 1/2 Mux, 1/3 Bias Drive ............................ 114
Type-B in 1/3 Mux, 1/2 Bias Drive ............................ 116
Type-B in 1/3 Mux, 1/3 Bias Drive ............................ 118
Type-B in 1/4 Mux, 1/3 Bias Drive ............................ 120
USART Synchronous Receive (Master/Slave) ......... 237
USART Synchronous Transmission (Master/Slave) . 236
Wake-up from Interrupt ............................................. 202
I
I2C Bus Start/Stop Bits ............................................. 243
SPI Mode .................................................................. 242
2
2
2
2
2
2
2
C Bus Data ............................................................. 243
C Bus Start/Stop Bits.............................................. 242
C Reception (7-bit Address) ................................... 171
C Slave Mode (Transmission, 10-bit Address) ....... 174
C Slave Mode with SEN = 0 (Reception, 10-bit Ad-
C Transmission (7-bit Address) .............................. 173
C Bus Data ............................................................. 244
dress) ................................................................ 172
Case 1............................................................... 191
Case 2............................................................... 191
Case 3............................................................... 191
Preliminary
TRISA
TRISA Register................................................................... 44
TRISB
TRISB Register................................................................... 54
TRISC
TRISC Register................................................................... 63
TRISD
TRISD Register................................................................... 72
TRISE
TRISE Register................................................................... 77
Two-Speed Clock Start-up Mode........................................ 40
TXSTA Register
U
UA..................................................................................... 160
Update Address bit, UA .................................................... 160
USART.............................................................................. 127
Registers .................................................................... 43
Registers .................................................................... 53
Registers .................................................................... 63
Registers .................................................................... 72
Registers .................................................................... 77
BRGH Bit .................................................................. 127
CSRC Bit .................................................................. 127
SYNC Bit .................................................................. 127
TRMT Bit................................................................... 127
TX9 Bit ...................................................................... 127
TX9D Bit ................................................................... 127
TXEN Bit ................................................................... 127
Address Detect Enable (ADDEN Bit)........................ 128
Asynchronous Mode ................................................. 131
Asynchronous Receive (9-bit Mode)......................... 136
Asynchronous Receive with Address Detect.
Asynchronous Receiver............................................ 134
Asynchronous Reception.......................................... 134
Asynchronous Transmitter........................................ 131
Baud Rate Generator (BRG) .................................... 129
Clock Source Select (CSRC Bit)............................... 127
Continuous Receive Enable (CREN Bit)................... 128
Framing Error (FERR Bit) ......................................... 128
Mode Select (SYNC Bit) ........................................... 127
Overrun Error (OERR Bit)......................................... 128
Receive Data, 9th Bit (RX9D Bit).............................. 128
Receive Enable, 9-bit (RX9 Bit) ................................ 128
Serial Port Enable (SPEN Bit) .......................... 127, 128
Single Receive Enable (SREN Bit) ........................... 128
Synchronous Master Mode....................................... 138
Synchronous Master Reception................................ 140
Synchronous Master Transmission .......................... 138
Synchronous Slave Mode......................................... 141
Synchronous Slave Reception.................................. 142
Synchronous Slave Transmit.................................... 141
Transmit Data, 9th Bit (TX9D) .................................. 127
Transmit Enable (TXEN Bit) ..................................... 127
Transmit Enable, Nine-bit (TX9 Bit) .......................... 127
Transmit Shift Register Status (TRMT Bit) ............... 127
See Asynchronous Receive (9-bit Mode).
Baud Rate Formula .......................................... 129
Baud Rates, Asynchronous Mode (BRGH = 0) 130
Baud Rates, Asynchronous Mode (BRGH = 1) 130
High Baud Rate Select (BRGH Bit) .................. 127
Sampling........................................................... 129
Requirements, Synchronous Receive .............. 237
Requirements, Synchronous Transmission...... 237
Timing Diagram, Synchronous Receive ........... 237
Timing Diagram, Synchronous Transmission... 236
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