PIC18F1230-I/P Microchip Technology, PIC18F1230-I/P Datasheet - Page 156
![IC PIC MCU FLASH 2KX16 18DIP](/photos/6/76/67657/18-dip_300mil__sml.jpg)
PIC18F1230-I/P
Manufacturer Part Number
PIC18F1230-I/P
Description
IC PIC MCU FLASH 2KX16 18DIP
Manufacturer
Microchip Technology
Series
PIC® 18Fr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.AC162078.pdf
(318 pages)
3.PIC18F1230-ISO.pdf
(6 pages)
4.PIC18F1230-ISO.pdf
(12 pages)
5.PIC18F1230-ISO.pdf
(4 pages)
6.PIC18F1230-IP.pdf
(312 pages)
Specifications of PIC18F1230-I/P
Program Memory Type
FLASH
Program Memory Size
4KB (2K x 16)
Package / Case
18-DIP (0.300", 7.62mm)
Core Processor
PIC
Core Size
8-Bit
Speed
40MHz
Connectivity
UART/USART
Peripherals
Brown-out Detect/Reset, LVD, POR, PWM, WDT
Number Of I /o
16
Eeprom Size
128 x 8
Ram Size
256 x 8
Voltage - Supply (vcc/vdd)
4.2 V ~ 5.5 V
Data Converters
A/D 4x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
PIC18F
Core
PIC
Data Bus Width
8 bit
Data Ram Size
256 B
Interface Type
EUSART
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
16
Number Of Timers
2
Operating Supply Voltage
5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
Through Hole
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, DV164136
Minimum Operating Temperature
- 40 C
On-chip Adc
4-ch x 10-bit
Package
18PDIP
Device Core
PIC
Family Name
PIC18
Maximum Speed
40 MHz
Height
3.3 mm
Length
22.86 mm
Supply Voltage (max)
5.5 V
Supply Voltage (min)
4.2 V
Width
6.35 mm
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC18F1230-I/P
Manufacturer:
MICROCHIP
Quantity:
5
Part Number:
PIC18F1230-I/P
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
- PIC16F616T-ISL PDF datasheet
- AC162078 PDF datasheet #2
- PIC18F1230-ISO PDF datasheet #3
- PIC18F1230-ISO PDF datasheet #4
- PIC18F1230-ISO PDF datasheet #5
- PIC18F1230-IP PDF datasheet #6
- Current page: 156 of 312
- Download datasheet (6Mb)
PIC18F1230/1330
FIGURE 14-7:
TABLE 14-6:
14.2.4
During Sleep mode, all clocks to the EUSART are
suspended. Because of this, the Baud Rate Generator
is inactive and a proper byte reception cannot be
performed. The auto-wake-up feature allows the
controller to wake-up due to activity on the RX/DT line
while the EUSART is operating in Asynchronous mode.
The auto-wake-up feature is enabled by setting the
WUE bit (BAUDCON<1>). Once set, the typical receive
sequence on RX/DT is disabled and the EUSART
remains in an Idle state, monitoring for a wake-up event
independent of the CPU mode. A wake-up event
consists of a high-to-low transition on the RX/DT line.
(This coincides with the start of a Sync Break or a
Wake-up Signal character for the LIN protocol.)
DS39758C-page 154
INTCON
PIR1
PIE1
IPR1
RCSTA
RCREG
TXSTA
BAUDCON
SPBRGH
SPBRG
Legend: — = unimplemented locations read as ‘0’. Shaded cells are not used for asynchronous reception.
Name
Note:
Rcv Buffer Reg
(Interrupt Flag)
Rcv Shift Reg
Buffer Reg
Read Rcv
OERR bit
RX (pin)
RCREG
This timing diagram shows three words appearing on the RX input. The RCREG (Receive Buffer) is read after the third word causing
the OERR (Overrun) bit to be set.
AUTO-WAKE-UP ON SYNC
BREAK CHARACTER
CREN
RCIF
EUSART Receive Register
EUSART Baud Rate Generator Register High Byte
EUSART Baud Rate Generator Register Low Byte
GIE/GIEH PEIE/GIEL
ABDOVF
SPEN
CSRC
Bit 7
REGISTERS ASSOCIATED WITH ASYNCHRONOUS RECEPTION
—
—
—
ASYNCHRONOUS RECEPTION
Start
bit
bit 0
RCIDL
ADIF
ADIE
ADIP
Bit 6
RX9
TX9
bit 1
TMR0IE
SREN
TXEN
RCIF
RCIE
RCIP
Bit 5
—
Advance Information
bit 7/8
Stop
INT0IE
CREN
SYNC
bit
SCKP
TXIE
TXIP
Bit 4
TXIF
Word 1
RCREG
Start
bit
CMP2IF
CMP2IE
CMP2IP
bit 0
ADDEN
SENDB
BRG16
Following a wake-up event, the module generates an
RCIF
synchronously to the Q clocks in normal operating
modes (Figure 14-8) and asynchronously if the device
is in Sleep mode (Figure 14-9). The interrupt condition
is cleared by reading the RCREG register.
The WUE bit is automatically cleared once a low-to-
high transition is observed on the RX line following the
wake-up event. At this point, the EUSART module is in
Idle mode and returns to normal operation. This signals
to the user that the Sync Break event is over.
RBIE
Bit 3
interrupt.
CMP1IE
CMP1IP
TMR0IF
CMP1IF
bit 7/8
BRGH
Word 2
RCREG
FERR
Bit 2
—
Stop
bit
The
CMP0IF
CMP0IE
CMP0IP
INT0IF
OERR
TRMT
Start
© 2007 Microchip Technology Inc.
WUE
Bit 1
bit
interrupt
TMR1IF
TMR1IE
TMR1IP
ABDEN
RX9D
TX9D
bit 7/8
RBIF
Bit 0
is
Stop
bit
generated
on Page:
Values
Reset
41
43
43
43
42
42
42
42
42
42
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