PIC18F1230-I/P Microchip Technology, PIC18F1230-I/P Datasheet - Page 23
![IC PIC MCU FLASH 2KX16 18DIP](/photos/6/76/67657/18-dip_300mil__sml.jpg)
PIC18F1230-I/P
Manufacturer Part Number
PIC18F1230-I/P
Description
IC PIC MCU FLASH 2KX16 18DIP
Manufacturer
Microchip Technology
Series
PIC® 18Fr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.AC162078.pdf
(318 pages)
3.PIC18F1230-ISO.pdf
(6 pages)
4.PIC18F1230-ISO.pdf
(12 pages)
5.PIC18F1230-ISO.pdf
(4 pages)
6.PIC18F1230-IP.pdf
(312 pages)
Specifications of PIC18F1230-I/P
Program Memory Type
FLASH
Program Memory Size
4KB (2K x 16)
Package / Case
18-DIP (0.300", 7.62mm)
Core Processor
PIC
Core Size
8-Bit
Speed
40MHz
Connectivity
UART/USART
Peripherals
Brown-out Detect/Reset, LVD, POR, PWM, WDT
Number Of I /o
16
Eeprom Size
128 x 8
Ram Size
256 x 8
Voltage - Supply (vcc/vdd)
4.2 V ~ 5.5 V
Data Converters
A/D 4x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
PIC18F
Core
PIC
Data Bus Width
8 bit
Data Ram Size
256 B
Interface Type
EUSART
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
16
Number Of Timers
2
Operating Supply Voltage
5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
Through Hole
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, DV164136
Minimum Operating Temperature
- 40 C
On-chip Adc
4-ch x 10-bit
Package
18PDIP
Device Core
PIC
Family Name
PIC18
Maximum Speed
40 MHz
Height
3.3 mm
Length
22.86 mm
Supply Voltage (max)
5.5 V
Supply Voltage (min)
4.2 V
Width
6.35 mm
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC18F1230-I/P
Manufacturer:
MICROCHIP
Quantity:
5
Part Number:
PIC18F1230-I/P
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
2.7.1
The OSCCON register (Register 2-2) controls several
aspects of the device clock’s operation, both in full
power operation and in power-managed modes.
The System Clock Select bits, SCS1:SCS0, select the
clock source. The available clock sources are the
primary
Configuration bits), the secondary clock (Timer1
oscillator) and the internal oscillator block. The clock
source changes immediately after one or more of the
bits is written to, following a brief clock transition
interval. The SCS bits are cleared on all forms of Reset.
The
(IRCF2:IRCF0) select the frequency output of the
internal oscillator block to drive the device clock. The
choices are the INTRC source, the INTOSC source
(8 MHz) or one of the frequencies derived from the
INTOSC postscaler (31.25 kHz to 4 MHz). If the
internal oscillator block is supplying the device clock,
changing the states of these bits will have an immedi-
ate change on the internal oscillator’s output. On
device Resets, the default output frequency of the
internal oscillator block is set at 1 MHz.
When a nominal output frequency of 31 kHz is selected
(IRCF2:IRCF0 = 000), users may choose which
internal oscillator acts as the source. This is done with
the
(OSCTUNE<7>). Setting this bit selects INTOSC as a
31.25 kHz clock source by enabling the divide-by-256
output of the INTOSC postscaler. Clearing INTSRC
selects INTRC (nominally 31 kHz) as the clock source.
This option allows users to select the tunable and more
precise INTOSC as a clock source, while maintaining
power savings with a very low clock speed. Regardless
of the setting of INTSRC, INTRC always remains the
clock source for features such as the Watchdog Timer
and the Fail-Safe Clock Monitor.
The OSTS, IOFS and T1RUN bits indicate which clock
source is currently providing the device clock. The
OSTS bit indicates that the Oscillator Start-up Timer
has timed out and the primary clock is providing the
device clock in primary clock modes. The IOFS bit
indicates when the internal oscillator block has
stabilized and is providing the device clock in RC Clock
modes. The T1RUN bit (T1CON<6>) indicates when
the Timer1 oscillator is providing the device clock in
secondary clock modes. In power-managed modes,
only one of these three bits will be set at any time. If
none of these bits are set, the INTRC is providing the
clock or the internal oscillator block has just started and
is not yet stable.
© 2007 Microchip Technology Inc.
INTSRC
Internal
clock
OSCILLATOR CONTROL REGISTER
Oscillator
bit
(defined
in
the
by
Frequency
OSCTUNE
the
FOSC3:FOSC0
Select
Advance Information
register
bits
The IDLEN bit determines if the device goes into Sleep
mode or one of the Idle modes when the SLEEP
instruction is executed.
The use of the flag and control bits in the OSCCON
register is discussed in more detail in Section 3.0
“Power-Managed Modes”.
2.7.2
PIC18F1230/1330 devices contain circuitry to prevent
clock “glitches” when switching between clock sources.
A short pause in the device clock occurs during the
clock switch. The length of this pause is the sum of two
cycles of the old clock source and three to four cycles
of the new clock source. This formula assumes that the
new clock source is stable.
Clock transitions are discussed in greater detail in
Section 3.1.2 “Entering Power-Managed Modes”.
Note 1: The Timer1 oscillator must be enabled to
2: It is recommended that the Timer1
PIC18F1230/1330
OSCILLATOR TRANSITIONS
select the secondary clock source. The
Timer1 oscillator is enabled by setting the
T1OSCEN bit in the Timer1 Control regis-
ter (T1CON<3>). If the Timer1 oscillator
is not enabled, then any attempt to select
a secondary clock source will be ignored.
oscillator be operating and stable before
selecting the secondary clock source or a
very long delay may occur while the
Timer1 oscillator starts.
DS39758C-page 21