ATMEGA8515L-8PU Atmel, ATMEGA8515L-8PU Datasheet - Page 151

• Manufacturer Part Number: ATMEGA8515L-8PU
• Description: IC AVR MCU 8K 8MHZ 3V 40DIP
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA8515L-8PU

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: EBI/EMI, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 35
• Program Memory Size: 8KB (4K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 512 x 8
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 40-DIP (0.600", 15.24mm)
• Processor Series: ATMEGA8x
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 512 B
• Interface Type: SPI, USART
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 35
• Number Of Timers: 2
• Operating Supply Voltage: 2.7 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: Through Hole
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Minimum Operating Temperature: - 40 C
• Cpu Family: ATmega
• Device Core: AVR
• Device Core Size: 8b
• Frequency (max): 8MHz
• Total Internal Ram Size: 512Byte
• # I/os (max): 35
• Number Of Timers - General Purpose: 2
• Operating Supply Voltage (typ): 3.3/5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 2.7V
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Through Hole
• Pin Count: 40
• Package Type: PDIP W
• Controller Family/series: AVR MEGA
• No. Of I/o's: 35
• Eeprom Memory Size: 512Byte
• Ram Memory Size: 512Byte
• Cpu Speed: 8MHz
• Rohs Compliant: Yes
• For Use With: ATSTK600-DIP40 - STK600 SOCKET/ADAPTER 40-PDIP770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAGATAVRISP2 - PROGRAMMER AVR IN SYSTEMATSTK500 - PROGRAMMER AVR STARTER KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Multi-processor
Communication Mode
2512K–AVR–01/10
Table 61. Recommended Maximum Receiver Baud Rate Error for Normal Speed Mode
(U2X = 0)
Table 62. Recommended Maximum Receiver Baud Rate Error for Double Speed Mode
(U2X = 1)
The recommendations of the maximum Receiver Baud Rate error was made under the
assumption that the Receiver and Transmitter equally divides the maximum total error.
There are two possible sources for the Receiver’s baud rate error. The Receiver’s sys-
tem clock (XTAL) will always have some minor instability over the supply voltage range
and the temperature range. When using a crystal to generate the system clock, this is
rarely a problem, but for a resonator the system clock may differ more than 2% depend-
ing of the resonators tolerance. The second source for the error is more controllable.
The baud rate generator can not always do an exact division of the system frequency to
get the baud rate wanted. In this case an UBRR value that gives an acceptable low error
can be used if possible.
Setting the Multi-processor Communication mode (MPCM) bit in UCSRA enables a fil-
tering function of incoming frames received by the USART Receiver. Frames that do not
contain address information will be ignored and not put into the receive buffer. This
effectively reduces the number of incoming frames that has to be handled by the CPU,
in a system with multiple MCUs that communicate via the same serial bus. The Trans-
mitter is unaffected by the MPCM setting, but has to be used differently when it is a part
of a system utilizing the Multi-processor Communication mode.
If the Receiver is set up to receive frames that contain 5 to 8 data bits, then the first stop
bit indicates if the frame contains data or address information. If the Receiver is set up
for frames with nine data bits, then the ninth bit (RXB8) is used for identifying address
and data frames. When the frame type bit (the first stop or the ninth bit) is one, the frame
contains an address. When the frame type bit is zero the frame is a data frame.
# (Data+Parity Bit)
# (Data+Parity Bit)
10
10
D
5
6
7
8
9
D
5
6
7
8
9
R
R
slow
93.20
94.12
94.81
95.36
95.81
96.17
slow
94.12
94.92
95.52
96.00
96.39
96.70
(%)
(%)
R
R
106.67
105.79
105.11
104.58
104.14
103.78
105.66
104.92
104.35
103.90
103.53
103.23
fast
fast
(%)
(%)
+5.79/-5.88
+5.11/-5.19
+4.58/-4.54
+4.14/-4.19
+3.78/-3.83
+5.66/-5.88
+4.92/-5.08
+4.32/-4.48
+3.90/-4.00
+3.53/-3.61
+3.23/-3.30
Max Total
+6.67/-6.8
Max Total
Error (%)
Error (%)
ATmega8515(L)
Recommended Max
Recommended Max
Receiver Error (%)
Receiver Error (%)
± 3.0
± 2.5
± 2.0
± 2.0
± 1.5
± 1.5
± 2.5
± 2.0
± 1.5
± 1.5
± 1.5
± 1.0
151